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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit multiplication in vector registers on z173;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s5 6; Multiplication.7define i128 @f1(i128 %a, i128 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r4), 311; CHECK-NEXT: vl %v1, 0(%r3), 312; CHECK-NEXT: vmlq %v0, %v1, %v013; CHECK-NEXT: vst %v0, 0(%r2), 314; CHECK-NEXT: br %r1415 %res = mul i128 %a, %b16 ret i128 %res17}18 19; Multiply-and-add.20define i128 @f2(i128 %a, i128 %b, i128 %add) {21; CHECK-LABEL: f2:22; CHECK: # %bb.0:23; CHECK-NEXT: vl %v0, 0(%r5), 324; CHECK-NEXT: vl %v1, 0(%r4), 325; CHECK-NEXT: vl %v2, 0(%r3), 326; CHECK-NEXT: vmalq %v0, %v2, %v1, %v027; CHECK-NEXT: vst %v0, 0(%r2), 328; CHECK-NEXT: br %r1429 %mul = mul i128 %a, %b30 %res = add i128 %mul, %add31 ret i128 %res32}33