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1; Test additions between an i64 and a sign-extended i32.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5declare i64 @foo()6 7; Check AGFR.8define zeroext i1 @f1(i64 %dummy, i64 %a, i32 %b, ptr %res) {9; CHECK-LABEL: f1:10; CHECK: agfr %r3, %r411; CHECK-DAG: stg %r3, 0(%r5)12; CHECK-DAG: ipm [[REG:%r[0-5]]]13; CHECK-DAG: afi [[REG]], 134217728014; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 3315; CHECK: br %r1416 %bext = sext i32 %b to i6417 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)18 %val = extractvalue {i64, i1} %t, 019 %obit = extractvalue {i64, i1} %t, 120 store i64 %val, ptr %res21 ret i1 %obit22}23 24; Check using the overflow result for a branch.25define void @f2(i64 %dummy, i64 %a, i32 %b, ptr %res) {26; CHECK-LABEL: f2:27; CHECK: agfr %r3, %r428; CHECK: stg %r3, 0(%r5)29; CHECK: jgo foo@PLT30; CHECK: br %r1431 %bext = sext i32 %b to i6432 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)33 %val = extractvalue {i64, i1} %t, 034 %obit = extractvalue {i64, i1} %t, 135 store i64 %val, ptr %res36 br i1 %obit, label %call, label %exit37 38call:39 tail call i64 @foo()40 br label %exit41 42exit:43 ret void44}45 46; ... and the same with the inverted direction.47define void @f3(i64 %dummy, i64 %a, i32 %b, ptr %res) {48; CHECK-LABEL: f3:49; CHECK: agfr %r3, %r450; CHECK: stg %r3, 0(%r5)51; CHECK: jgno foo@PLT52; CHECK: br %r1453 %bext = sext i32 %b to i6454 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)55 %val = extractvalue {i64, i1} %t, 056 %obit = extractvalue {i64, i1} %t, 157 store i64 %val, ptr %res58 br i1 %obit, label %exit, label %call59 60call:61 tail call i64 @foo()62 br label %exit63 64exit:65 ret void66}67 68; Check AGF with no displacement.69define zeroext i1 @f4(i64 %dummy, i64 %a, ptr %src, ptr %res) {70; CHECK-LABEL: f4:71; CHECK: agf %r3, 0(%r4)72; CHECK-DAG: stg %r3, 0(%r5)73; CHECK-DAG: ipm [[REG:%r[0-5]]]74; CHECK-DAG: afi [[REG]], 134217728075; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 3376; CHECK: br %r1477 %b = load i32, ptr %src78 %bext = sext i32 %b to i6479 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)80 %val = extractvalue {i64, i1} %t, 081 %obit = extractvalue {i64, i1} %t, 182 store i64 %val, ptr %res83 ret i1 %obit84}85 86; Check the high end of the aligned AGF range.87define zeroext i1 @f5(i64 %dummy, i64 %a, ptr %src, ptr %res) {88; CHECK-LABEL: f5:89; CHECK: agf %r3, 524284(%r4)90; CHECK-DAG: stg %r3, 0(%r5)91; CHECK-DAG: ipm [[REG:%r[0-5]]]92; CHECK-DAG: afi [[REG]], 134217728093; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 3394; CHECK: br %r1495 %ptr = getelementptr i32, ptr %src, i64 13107196 %b = load i32, ptr %ptr97 %bext = sext i32 %b to i6498 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)99 %val = extractvalue {i64, i1} %t, 0100 %obit = extractvalue {i64, i1} %t, 1101 store i64 %val, ptr %res102 ret i1 %obit103}104 105; Check the next word up, which needs separate address logic.106; Other sequences besides this one would be OK.107define zeroext i1 @f6(i64 %dummy, i64 %a, ptr %src, ptr %res) {108; CHECK-LABEL: f6:109; CHECK: agfi %r4, 524288110; CHECK: agf %r3, 0(%r4)111; CHECK-DAG: stg %r3, 0(%r5)112; CHECK-DAG: ipm [[REG:%r[0-5]]]113; CHECK-DAG: afi [[REG]], 1342177280114; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33115; CHECK: br %r14116 %ptr = getelementptr i32, ptr %src, i64 131072117 %b = load i32, ptr %ptr118 %bext = sext i32 %b to i64119 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)120 %val = extractvalue {i64, i1} %t, 0121 %obit = extractvalue {i64, i1} %t, 1122 store i64 %val, ptr %res123 ret i1 %obit124}125 126; Check the high end of the negative aligned AGF range.127define zeroext i1 @f7(i64 %dummy, i64 %a, ptr %src, ptr %res) {128; CHECK-LABEL: f7:129; CHECK: agf %r3, -4(%r4)130; CHECK-DAG: stg %r3, 0(%r5)131; CHECK-DAG: ipm [[REG:%r[0-5]]]132; CHECK-DAG: afi [[REG]], 1342177280133; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33134; CHECK: br %r14135 %ptr = getelementptr i32, ptr %src, i64 -1136 %b = load i32, ptr %ptr137 %bext = sext i32 %b to i64138 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)139 %val = extractvalue {i64, i1} %t, 0140 %obit = extractvalue {i64, i1} %t, 1141 store i64 %val, ptr %res142 ret i1 %obit143}144 145; Check the low end of the AGF range.146define zeroext i1 @f8(i64 %dummy, i64 %a, ptr %src, ptr %res) {147; CHECK-LABEL: f8:148; CHECK: agf %r3, -524288(%r4)149; CHECK-DAG: stg %r3, 0(%r5)150; CHECK-DAG: ipm [[REG:%r[0-5]]]151; CHECK-DAG: afi [[REG]], 1342177280152; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33153; CHECK: br %r14154 %ptr = getelementptr i32, ptr %src, i64 -131072155 %b = load i32, ptr %ptr156 %bext = sext i32 %b to i64157 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)158 %val = extractvalue {i64, i1} %t, 0159 %obit = extractvalue {i64, i1} %t, 1160 store i64 %val, ptr %res161 ret i1 %obit162}163 164; Check the next word down, which needs separate address logic.165; Other sequences besides this one would be OK.166define zeroext i1 @f9(i64 %dummy, i64 %a, ptr %src, ptr %res) {167; CHECK-LABEL: f9:168; CHECK: agfi %r4, -524292169; CHECK: agf %r3, 0(%r4)170; CHECK-DAG: stg %r3, 0(%r5)171; CHECK-DAG: ipm [[REG:%r[0-5]]]172; CHECK-DAG: afi [[REG]], 1342177280173; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33174; CHECK: br %r14175 %ptr = getelementptr i32, ptr %src, i64 -131073176 %b = load i32, ptr %ptr177 %bext = sext i32 %b to i64178 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)179 %val = extractvalue {i64, i1} %t, 0180 %obit = extractvalue {i64, i1} %t, 1181 store i64 %val, ptr %res182 ret i1 %obit183}184 185; Check that AGF allows an index.186define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, ptr %res) {187; CHECK-LABEL: f10:188; CHECK: agf %r4, 524284({{%r3,%r2|%r2,%r3}})189; CHECK-DAG: stg %r4, 0(%r5)190; CHECK-DAG: ipm [[REG:%r[0-5]]]191; CHECK-DAG: afi [[REG]], 1342177280192; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33193; CHECK: br %r14194 %add1 = add i64 %src, %index195 %add2 = add i64 %add1, 524284196 %ptr = inttoptr i64 %add2 to ptr197 %b = load i32, ptr %ptr198 %bext = sext i32 %b to i64199 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 %bext)200 %val = extractvalue {i64, i1} %t, 0201 %obit = extractvalue {i64, i1} %t, 1202 store i64 %val, ptr %res203 ret i1 %obit204}205 206; Check that additions of spilled values can use AGF rather than AGFR.207define zeroext i1 @f11(ptr %ptr0) {208; CHECK-LABEL: f11:209; CHECK: brasl %r14, foo@PLT210; CHECK: agf %r2, 16{{[04]}}(%r15)211; CHECK: br %r14212 %ptr1 = getelementptr i32, ptr %ptr0, i64 2213 %ptr2 = getelementptr i32, ptr %ptr0, i64 4214 %ptr3 = getelementptr i32, ptr %ptr0, i64 6215 %ptr4 = getelementptr i32, ptr %ptr0, i64 8216 %ptr5 = getelementptr i32, ptr %ptr0, i64 10217 %ptr6 = getelementptr i32, ptr %ptr0, i64 12218 %ptr7 = getelementptr i32, ptr %ptr0, i64 14219 %ptr8 = getelementptr i32, ptr %ptr0, i64 16220 %ptr9 = getelementptr i32, ptr %ptr0, i64 18221 222 %val0 = load i32, ptr %ptr0223 %val1 = load i32, ptr %ptr1224 %val2 = load i32, ptr %ptr2225 %val3 = load i32, ptr %ptr3226 %val4 = load i32, ptr %ptr4227 %val5 = load i32, ptr %ptr5228 %val6 = load i32, ptr %ptr6229 %val7 = load i32, ptr %ptr7230 %val8 = load i32, ptr %ptr8231 %val9 = load i32, ptr %ptr9232 233 %frob0 = add i32 %val0, 100234 %frob1 = add i32 %val1, 100235 %frob2 = add i32 %val2, 100236 %frob3 = add i32 %val3, 100237 %frob4 = add i32 %val4, 100238 %frob5 = add i32 %val5, 100239 %frob6 = add i32 %val6, 100240 %frob7 = add i32 %val7, 100241 %frob8 = add i32 %val8, 100242 %frob9 = add i32 %val9, 100243 244 store i32 %frob0, ptr %ptr0245 store i32 %frob1, ptr %ptr1246 store i32 %frob2, ptr %ptr2247 store i32 %frob3, ptr %ptr3248 store i32 %frob4, ptr %ptr4249 store i32 %frob5, ptr %ptr5250 store i32 %frob6, ptr %ptr6251 store i32 %frob7, ptr %ptr7252 store i32 %frob8, ptr %ptr8253 store i32 %frob9, ptr %ptr9254 255 %ret = call i64 @foo()256 257 %ext0 = sext i32 %frob0 to i64258 %ext1 = sext i32 %frob1 to i64259 %ext2 = sext i32 %frob2 to i64260 %ext3 = sext i32 %frob3 to i64261 %ext4 = sext i32 %frob4 to i64262 %ext5 = sext i32 %frob5 to i64263 %ext6 = sext i32 %frob6 to i64264 %ext7 = sext i32 %frob7 to i64265 %ext8 = sext i32 %frob8 to i64266 %ext9 = sext i32 %frob9 to i64267 268 %t0 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %ret, i64 %ext0)269 %add0 = extractvalue {i64, i1} %t0, 0270 %obit0 = extractvalue {i64, i1} %t0, 1271 %t1 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add0, i64 %ext1)272 %add1 = extractvalue {i64, i1} %t1, 0273 %obit1 = extractvalue {i64, i1} %t1, 1274 %res1 = or i1 %obit0, %obit1275 %t2 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add1, i64 %ext2)276 %add2 = extractvalue {i64, i1} %t2, 0277 %obit2 = extractvalue {i64, i1} %t2, 1278 %res2 = or i1 %res1, %obit2279 %t3 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add2, i64 %ext3)280 %add3 = extractvalue {i64, i1} %t3, 0281 %obit3 = extractvalue {i64, i1} %t3, 1282 %res3 = or i1 %res2, %obit3283 %t4 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add3, i64 %ext4)284 %add4 = extractvalue {i64, i1} %t4, 0285 %obit4 = extractvalue {i64, i1} %t4, 1286 %res4 = or i1 %res3, %obit4287 %t5 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add4, i64 %ext5)288 %add5 = extractvalue {i64, i1} %t5, 0289 %obit5 = extractvalue {i64, i1} %t5, 1290 %res5 = or i1 %res4, %obit5291 %t6 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add5, i64 %ext6)292 %add6 = extractvalue {i64, i1} %t6, 0293 %obit6 = extractvalue {i64, i1} %t6, 1294 %res6 = or i1 %res5, %obit6295 %t7 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add6, i64 %ext7)296 %add7 = extractvalue {i64, i1} %t7, 0297 %obit7 = extractvalue {i64, i1} %t7, 1298 %res7 = or i1 %res6, %obit7299 %t8 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add7, i64 %ext8)300 %add8 = extractvalue {i64, i1} %t8, 0301 %obit8 = extractvalue {i64, i1} %t8, 1302 %res8 = or i1 %res7, %obit8303 %t9 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %add8, i64 %ext9)304 %add9 = extractvalue {i64, i1} %t9, 0305 %obit9 = extractvalue {i64, i1} %t9, 1306 %res9 = or i1 %res8, %obit9307 308 ret i1 %res9309}310 311declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone312 313