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1; Test 128-bit addition in which the second operand is a zero-extended i32.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5; Check register additions. The XOR ensures that we don't instead zero-extend6; %b into a register and use memory addition.7define void @f1(ptr %aptr, i32 %b) {8; CHECK-LABEL: f1:9; CHECK: slgfr {{%r[0-5]}}, %r310; CHECK: slbgr11; CHECK: br %r1412 %a = load i128, ptr %aptr13 %xor = xor i128 %a, 12714 %bext = zext i32 %b to i12815 %sub = sub i128 %xor, %bext16 store i128 %sub, ptr %aptr17 ret void18}19 20; Like f1, but using an "in-register" extension.21define void @f2(ptr %aptr, i64 %b) {22; CHECK-LABEL: f2:23; CHECK: slgfr {{%r[0-5]}}, %r324; CHECK: slbgr25; CHECK: br %r1426 %a = load i128, ptr %aptr27 %xor = xor i128 %a, 12728 %trunc = trunc i64 %b to i3229 %bext = zext i32 %trunc to i12830 %sub = sub i128 %xor, %bext31 store i128 %sub, ptr %aptr32 ret void33}34 35; Test register addition in cases where the second operand is zero extended36; from i64 rather than i32, but is later masked to i32 range.37define void @f3(ptr %aptr, i64 %b) {38; CHECK-LABEL: f3:39; CHECK: slgfr {{%r[0-5]}}, %r340; CHECK: slbgr41; CHECK: br %r1442 %a = load i128, ptr %aptr43 %xor = xor i128 %a, 12744 %bext = zext i64 %b to i12845 %and = and i128 %bext, 429496729546 %sub = sub i128 %xor, %and47 store i128 %sub, ptr %aptr48 ret void49}50 51; Test SLGF with no offset.52define void @f4(ptr %aptr, ptr %bsrc) {53; CHECK-LABEL: f4:54; CHECK: slgf {{%r[0-5]}}, 0(%r3)55; CHECK: slbgr56; CHECK: br %r1457 %a = load i128, ptr %aptr58 %xor = xor i128 %a, 12759 %b = load i32, ptr %bsrc60 %bext = zext i32 %b to i12861 %sub = sub i128 %xor, %bext62 store i128 %sub, ptr %aptr63 ret void64}65 66; Check the high end of the SLGF range.67define void @f5(ptr %aptr, ptr %bsrc) {68; CHECK-LABEL: f5:69; CHECK: slgf {{%r[0-5]}}, 524284(%r3)70; CHECK: slbgr71; CHECK: br %r1472 %a = load i128, ptr %aptr73 %xor = xor i128 %a, 12774 %ptr = getelementptr i32, ptr %bsrc, i64 13107175 %b = load i32, ptr %ptr76 %bext = zext i32 %b to i12877 %sub = sub i128 %xor, %bext78 store i128 %sub, ptr %aptr79 ret void80}81 82; Check the next word up, which must use separate address logic.83; Other sequences besides this one would be OK.84define void @f6(ptr %aptr, ptr %bsrc) {85; CHECK-LABEL: f6:86; CHECK: agfi %r3, 52428887; CHECK: slgf {{%r[0-5]}}, 0(%r3)88; CHECK: slbgr89; CHECK: br %r1490 %a = load i128, ptr %aptr91 %xor = xor i128 %a, 12792 %ptr = getelementptr i32, ptr %bsrc, i64 13107293 %b = load i32, ptr %ptr94 %bext = zext i32 %b to i12895 %sub = sub i128 %xor, %bext96 store i128 %sub, ptr %aptr97 ret void98}99 100; Check the high end of the negative aligned SLGF range.101define void @f7(ptr %aptr, ptr %bsrc) {102; CHECK-LABEL: f7:103; CHECK: slgf {{%r[0-5]}}, -4(%r3)104; CHECK: slbgr105; CHECK: br %r14106 %a = load i128, ptr %aptr107 %xor = xor i128 %a, 127108 %ptr = getelementptr i32, ptr %bsrc, i128 -1109 %b = load i32, ptr %ptr110 %bext = zext i32 %b to i128111 %sub = sub i128 %xor, %bext112 store i128 %sub, ptr %aptr113 ret void114}115 116; Check the low end of the SLGF range.117define void @f8(ptr %aptr, ptr %bsrc) {118; CHECK-LABEL: f8:119; CHECK: slgf {{%r[0-5]}}, -524288(%r3)120; CHECK: slbgr121; CHECK: br %r14122 %a = load i128, ptr %aptr123 %xor = xor i128 %a, 127124 %ptr = getelementptr i32, ptr %bsrc, i128 -131072125 %b = load i32, ptr %ptr126 %bext = zext i32 %b to i128127 %sub = sub i128 %xor, %bext128 store i128 %sub, ptr %aptr129 ret void130}131 132; Check the next word down, which needs separate address logic.133; Other sequences besides this one would be OK.134define void @f9(ptr %aptr, ptr %bsrc) {135; CHECK-LABEL: f9:136; CHECK: agfi %r3, -524292137; CHECK: slgf {{%r[0-5]}}, 0(%r3)138; CHECK: slbgr139; CHECK: br %r14140 %a = load i128, ptr %aptr141 %xor = xor i128 %a, 127142 %ptr = getelementptr i32, ptr %bsrc, i128 -131073143 %b = load i32, ptr %ptr144 %bext = zext i32 %b to i128145 %sub = sub i128 %xor, %bext146 store i128 %sub, ptr %aptr147 ret void148}149 150; Check that SLGF allows an index.151define void @f10(ptr %aptr, i64 %src, i64 %index) {152; CHECK-LABEL: f10:153; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})154; CHECK: br %r14155 %a = load i128, ptr %aptr156 %xor = xor i128 %a, 127157 %add1 = add i64 %src, %index158 %add2 = add i64 %add1, 524284159 %ptr = inttoptr i64 %add2 to ptr160 %b = load i32, ptr %ptr161 %bext = zext i32 %b to i128162 %sub = sub i128 %xor, %bext163 store i128 %sub, ptr %aptr164 ret void165}166