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1; Test 64-bit additions of constants to memory.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5declare i64 @foo()6 7; Check addition of 1.8define zeroext i1 @f1(ptr %ptr) {9; CHECK-LABEL: f1:10; CHECK: algsi 0(%r2), 111; CHECK: ipm [[REG:%r[0-5]]]12; CHECK: risbg %r2, [[REG]], 63, 191, 3513; CHECK: br %r1414 %a = load i64, ptr %ptr15 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)16 %val = extractvalue {i64, i1} %t, 017 %obit = extractvalue {i64, i1} %t, 118 store i64 %val, ptr %ptr19 ret i1 %obit20}21 22; Check the high end of the constant range.23define zeroext i1 @f2(ptr %ptr) {24; CHECK-LABEL: f2:25; CHECK: algsi 0(%r2), 12726; CHECK: ipm [[REG:%r[0-5]]]27; CHECK: risbg %r2, [[REG]], 63, 191, 3528; CHECK: br %r1429 %a = load i64, ptr %ptr30 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 127)31 %val = extractvalue {i64, i1} %t, 032 %obit = extractvalue {i64, i1} %t, 133 store i64 %val, ptr %ptr34 ret i1 %obit35}36 37; Check the next constant up, which must use an addition and a store.38define zeroext i1 @f3(i64 %dummy, ptr %ptr) {39; CHECK-LABEL: f3:40; CHECK: lg [[VAL:%r[0-5]]], 0(%r3)41; CHECK: algfi [[VAL]], 12842; CHECK-DAG: stg [[VAL]], 0(%r3)43; CHECK-DAG: ipm [[REG:%r[0-5]]]44; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 3545; CHECK: br %r1446 %a = load i64, ptr %ptr47 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 128)48 %val = extractvalue {i64, i1} %t, 049 %obit = extractvalue {i64, i1} %t, 150 store i64 %val, ptr %ptr51 ret i1 %obit52}53 54; Check the low end of the constant range.55define zeroext i1 @f4(ptr %ptr) {56; CHECK-LABEL: f4:57; CHECK: algsi 0(%r2), -12858; CHECK: ipm [[REG:%r[0-5]]]59; CHECK: risbg %r2, [[REG]], 63, 191, 3560; CHECK: br %r1461 %a = load i64, ptr %ptr62 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 -128)63 %val = extractvalue {i64, i1} %t, 064 %obit = extractvalue {i64, i1} %t, 165 store i64 %val, ptr %ptr66 ret i1 %obit67}68 69; Check the next value down, with the same comment as f3.70define zeroext i1 @f5(i64 %dummy, ptr %ptr) {71; CHECK-LABEL: f5:72; CHECK: lg [[VAL1:%r[0-5]]], 0(%r3)73; CHECK: lghi [[VAL2:%r[0-9]+]], -12974; CHECK: algr [[VAL2]], [[VAL1]]75; CHECK-DAG: stg [[VAL2]], 0(%r3)76; CHECK-DAG: ipm [[REG:%r[0-5]]]77; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 3578; CHECK: br %r1479 %a = load i64, ptr %ptr80 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 -129)81 %val = extractvalue {i64, i1} %t, 082 %obit = extractvalue {i64, i1} %t, 183 store i64 %val, ptr %ptr84 ret i1 %obit85}86 87; Check the high end of the aligned ALGSI range.88define zeroext i1 @f6(ptr %base) {89; CHECK-LABEL: f6:90; CHECK: algsi 524280(%r2), 191; CHECK: ipm [[REG:%r[0-5]]]92; CHECK: risbg %r2, [[REG]], 63, 191, 3593; CHECK: br %r1494 %ptr = getelementptr i64, ptr %base, i64 6553595 %a = load i64, ptr %ptr96 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)97 %val = extractvalue {i64, i1} %t, 098 %obit = extractvalue {i64, i1} %t, 199 store i64 %val, ptr %ptr100 ret i1 %obit101}102 103; Check the next word up, which must use separate address logic.104; Other sequences besides this one would be OK.105define zeroext i1 @f7(ptr %base) {106; CHECK-LABEL: f7:107; CHECK: agfi %r2, 524288108; CHECK: algsi 0(%r2), 1109; CHECK: ipm [[REG:%r[0-5]]]110; CHECK: risbg %r2, [[REG]], 63, 191, 35111; CHECK: br %r14112 %ptr = getelementptr i64, ptr %base, i64 65536113 %a = load i64, ptr %ptr114 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)115 %val = extractvalue {i64, i1} %t, 0116 %obit = extractvalue {i64, i1} %t, 1117 store i64 %val, ptr %ptr118 ret i1 %obit119}120 121; Check the low end of the ALGSI range.122define zeroext i1 @f8(ptr %base) {123; CHECK-LABEL: f8:124; CHECK: algsi -524288(%r2), 1125; CHECK: ipm [[REG:%r[0-5]]]126; CHECK: risbg %r2, [[REG]], 63, 191, 35127; CHECK: br %r14128 %ptr = getelementptr i64, ptr %base, i64 -65536129 %a = load i64, ptr %ptr130 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)131 %val = extractvalue {i64, i1} %t, 0132 %obit = extractvalue {i64, i1} %t, 1133 store i64 %val, ptr %ptr134 ret i1 %obit135}136 137; Check the next word down, which must use separate address logic.138; Other sequences besides this one would be OK.139define zeroext i1 @f9(ptr %base) {140; CHECK-LABEL: f9:141; CHECK: agfi %r2, -524296142; CHECK: algsi 0(%r2), 1143; CHECK: ipm [[REG:%r[0-5]]]144; CHECK: risbg %r2, [[REG]], 63, 191, 35145; CHECK: br %r14146 %ptr = getelementptr i64, ptr %base, i64 -65537147 %a = load i64, ptr %ptr148 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)149 %val = extractvalue {i64, i1} %t, 0150 %obit = extractvalue {i64, i1} %t, 1151 store i64 %val, ptr %ptr152 ret i1 %obit153}154 155; Check that ALGSI does not allow indices.156define zeroext i1 @f10(i64 %base, i64 %index) {157; CHECK-LABEL: f10:158; CHECK: agr %r2, %r3159; CHECK: algsi 8(%r2), 1160; CHECK: ipm [[REG:%r[0-5]]]161; CHECK: risbg %r2, [[REG]], 63, 191, 35162; CHECK: br %r14163 %add1 = add i64 %base, %index164 %add2 = add i64 %add1, 8165 %ptr = inttoptr i64 %add2 to ptr166 %a = load i64, ptr %ptr167 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)168 %val = extractvalue {i64, i1} %t, 0169 %obit = extractvalue {i64, i1} %t, 1170 store i64 %val, ptr %ptr171 ret i1 %obit172}173 174; Check that adding 127 to a spilled value can use ALGSI.175define zeroext i1 @f11(ptr %ptr, i64 %sel) {176; CHECK-LABEL: f11:177; CHECK: algsi {{[0-9]+}}(%r15), 127178; CHECK: br %r14179entry:180 %val0 = load volatile i64, ptr %ptr181 %val1 = load volatile i64, ptr %ptr182 %val2 = load volatile i64, ptr %ptr183 %val3 = load volatile i64, ptr %ptr184 %val4 = load volatile i64, ptr %ptr185 %val5 = load volatile i64, ptr %ptr186 %val6 = load volatile i64, ptr %ptr187 %val7 = load volatile i64, ptr %ptr188 %val8 = load volatile i64, ptr %ptr189 %val9 = load volatile i64, ptr %ptr190 %val10 = load volatile i64, ptr %ptr191 %val11 = load volatile i64, ptr %ptr192 %val12 = load volatile i64, ptr %ptr193 %val13 = load volatile i64, ptr %ptr194 %val14 = load volatile i64, ptr %ptr195 %val15 = load volatile i64, ptr %ptr196 197 %test = icmp ne i64 %sel, 0198 br i1 %test, label %add, label %store199 200add:201 %t0 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val0, i64 127)202 %add0 = extractvalue {i64, i1} %t0, 0203 %obit0 = extractvalue {i64, i1} %t0, 1204 %t1 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val1, i64 127)205 %add1 = extractvalue {i64, i1} %t1, 0206 %obit1 = extractvalue {i64, i1} %t1, 1207 %res1 = or i1 %obit0, %obit1208 %t2 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val2, i64 127)209 %add2 = extractvalue {i64, i1} %t2, 0210 %obit2 = extractvalue {i64, i1} %t2, 1211 %res2 = or i1 %res1, %obit2212 %t3 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val3, i64 127)213 %add3 = extractvalue {i64, i1} %t3, 0214 %obit3 = extractvalue {i64, i1} %t3, 1215 %res3 = or i1 %res2, %obit3216 %t4 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val4, i64 127)217 %add4 = extractvalue {i64, i1} %t4, 0218 %obit4 = extractvalue {i64, i1} %t4, 1219 %res4 = or i1 %res3, %obit4220 %t5 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val5, i64 127)221 %add5 = extractvalue {i64, i1} %t5, 0222 %obit5 = extractvalue {i64, i1} %t5, 1223 %res5 = or i1 %res4, %obit5224 %t6 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val6, i64 127)225 %add6 = extractvalue {i64, i1} %t6, 0226 %obit6 = extractvalue {i64, i1} %t6, 1227 %res6 = or i1 %res5, %obit6228 %t7 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val7, i64 127)229 %add7 = extractvalue {i64, i1} %t7, 0230 %obit7 = extractvalue {i64, i1} %t7, 1231 %res7 = or i1 %res6, %obit7232 %t8 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val8, i64 127)233 %add8 = extractvalue {i64, i1} %t8, 0234 %obit8 = extractvalue {i64, i1} %t8, 1235 %res8 = or i1 %res7, %obit8236 %t9 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val9, i64 127)237 %add9 = extractvalue {i64, i1} %t9, 0238 %obit9 = extractvalue {i64, i1} %t9, 1239 %res9 = or i1 %res8, %obit9240 %t10 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val10, i64 127)241 %add10 = extractvalue {i64, i1} %t10, 0242 %obit10 = extractvalue {i64, i1} %t10, 1243 %res10 = or i1 %res9, %obit10244 %t11 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val11, i64 127)245 %add11 = extractvalue {i64, i1} %t11, 0246 %obit11 = extractvalue {i64, i1} %t11, 1247 %res11 = or i1 %res10, %obit11248 %t12 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val12, i64 127)249 %add12 = extractvalue {i64, i1} %t12, 0250 %obit12 = extractvalue {i64, i1} %t12, 1251 %res12 = or i1 %res11, %obit12252 %t13 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val13, i64 127)253 %add13 = extractvalue {i64, i1} %t13, 0254 %obit13 = extractvalue {i64, i1} %t13, 1255 %res13 = or i1 %res12, %obit13256 %t14 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val14, i64 127)257 %add14 = extractvalue {i64, i1} %t14, 0258 %obit14 = extractvalue {i64, i1} %t14, 1259 %res14 = or i1 %res13, %obit14260 %t15 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %val15, i64 127)261 %add15 = extractvalue {i64, i1} %t15, 0262 %obit15 = extractvalue {i64, i1} %t15, 1263 %res15 = or i1 %res14, %obit15264 265 br label %store266 267store:268 %new0 = phi i64 [ %val0, %entry ], [ %add0, %add ]269 %new1 = phi i64 [ %val1, %entry ], [ %add1, %add ]270 %new2 = phi i64 [ %val2, %entry ], [ %add2, %add ]271 %new3 = phi i64 [ %val3, %entry ], [ %add3, %add ]272 %new4 = phi i64 [ %val4, %entry ], [ %add4, %add ]273 %new5 = phi i64 [ %val5, %entry ], [ %add5, %add ]274 %new6 = phi i64 [ %val6, %entry ], [ %add6, %add ]275 %new7 = phi i64 [ %val7, %entry ], [ %add7, %add ]276 %new8 = phi i64 [ %val8, %entry ], [ %add8, %add ]277 %new9 = phi i64 [ %val9, %entry ], [ %add9, %add ]278 %new10 = phi i64 [ %val10, %entry ], [ %add10, %add ]279 %new11 = phi i64 [ %val11, %entry ], [ %add11, %add ]280 %new12 = phi i64 [ %val12, %entry ], [ %add12, %add ]281 %new13 = phi i64 [ %val13, %entry ], [ %add13, %add ]282 %new14 = phi i64 [ %val14, %entry ], [ %add14, %add ]283 %new15 = phi i64 [ %val15, %entry ], [ %add15, %add ]284 %res = phi i1 [ 0, %entry ], [ %res15, %add ]285 286 store volatile i64 %new0, ptr %ptr287 store volatile i64 %new1, ptr %ptr288 store volatile i64 %new2, ptr %ptr289 store volatile i64 %new3, ptr %ptr290 store volatile i64 %new4, ptr %ptr291 store volatile i64 %new5, ptr %ptr292 store volatile i64 %new6, ptr %ptr293 store volatile i64 %new7, ptr %ptr294 store volatile i64 %new8, ptr %ptr295 store volatile i64 %new9, ptr %ptr296 store volatile i64 %new10, ptr %ptr297 store volatile i64 %new11, ptr %ptr298 store volatile i64 %new12, ptr %ptr299 store volatile i64 %new13, ptr %ptr300 store volatile i64 %new14, ptr %ptr301 store volatile i64 %new15, ptr %ptr302 303 ret i1 %res304}305 306; Check using the overflow result for a branch.307define void @f12(ptr %ptr) {308; CHECK-LABEL: f12:309; CHECK: algsi 0(%r2), 1310; CHECK: jgnle foo@PLT311; CHECK: br %r14312 %a = load i64, ptr %ptr313 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)314 %val = extractvalue {i64, i1} %t, 0315 %obit = extractvalue {i64, i1} %t, 1316 store i64 %val, ptr %ptr317 br i1 %obit, label %call, label %exit318 319call:320 tail call i64 @foo()321 br label %exit322 323exit:324 ret void325}326 327; ... and the same with the inverted direction.328define void @f13(ptr %ptr) {329; CHECK-LABEL: f13:330; CHECK: algsi 0(%r2), 1331; CHECK: jgle foo@PLT332; CHECK: br %r14333 %a = load i64, ptr %ptr334 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 1)335 %val = extractvalue {i64, i1} %t, 0336 %obit = extractvalue {i64, i1} %t, 1337 store i64 %val, ptr %ptr338 br i1 %obit, label %exit, label %call339 340call:341 tail call i64 @foo()342 br label %exit343 344exit:345 ret void346}347 348declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind 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