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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; Test 256-bit addition on z13 and higher3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6define zeroext i1 @f1(i256 %a, i256 %b, ptr %res) {7; CHECK-LABEL: f1:8; CHECK: # %bb.0:9; CHECK-NEXT: vl %v2, 16(%r3), 310; CHECK-NEXT: vl %v3, 16(%r2), 311; CHECK-NEXT: vl %v0, 0(%r3), 312; CHECK-NEXT: vl %v1, 0(%r2), 313; CHECK-NEXT: vaccq %v4, %v3, %v214; CHECK-NEXT: vacccq %v5, %v1, %v0, %v415; CHECK-NEXT: vlgvg %r2, %v5, 116; CHECK-NEXT: vacq %v0, %v1, %v0, %v417; CHECK-NEXT: vaq %v1, %v3, %v218; CHECK-NEXT: vst %v1, 16(%r4), 319; CHECK-NEXT: vst %v0, 0(%r4), 320; CHECK-NEXT: br %r1421 %t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)22 %val = extractvalue {i256, i1} %t, 023 %obit = extractvalue {i256, i1} %t, 124 store i256 %val, ptr %res25 ret i1 %obit26}27 28define zeroext i1 @f2(i256 %a, i256 %b) {29; CHECK-LABEL: f2:30; CHECK: # %bb.0:31; CHECK-NEXT: vl %v2, 16(%r3), 332; CHECK-NEXT: vl %v3, 16(%r2), 333; CHECK-NEXT: vl %v0, 0(%r3), 334; CHECK-NEXT: vl %v1, 0(%r2), 335; CHECK-NEXT: vaccq %v2, %v3, %v236; CHECK-NEXT: vacccq %v0, %v1, %v0, %v237; CHECK-NEXT: vlgvg %r2, %v0, 138; CHECK-NEXT: br %r1439 %t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)40 %obit = extractvalue {i256, i1} %t, 141 ret i1 %obit42}43 44define i256 @f3(i256 %a, i256 %b) {45; CHECK-LABEL: f3:46; CHECK: # %bb.0:47; CHECK-NEXT: vl %v2, 16(%r4), 348; CHECK-NEXT: vl %v3, 16(%r3), 349; CHECK-NEXT: vl %v0, 0(%r4), 350; CHECK-NEXT: vl %v1, 0(%r3), 351; CHECK-NEXT: vaccq %v4, %v3, %v252; CHECK-NEXT: vacq %v0, %v1, %v0, %v453; CHECK-NEXT: vaq %v1, %v3, %v254; CHECK-NEXT: vst %v1, 16(%r2), 355; CHECK-NEXT: vst %v0, 0(%r2), 356; CHECK-NEXT: br %r1457 %t = call {i256, i1} @llvm.uadd.with.overflow.i256(i256 %a, i256 %b)58 %val = extractvalue {i256, i1} %t, 059 ret i256 %val60}61 62declare {i256, i1} @llvm.uadd.with.overflow.i256(i256, i256) nounwind readnone63 64