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1# Check that the extra operand for the full register added by RegAlloc does2# not have a latency that interferes with the latency adjustment3# (ReadAdvance) for the MSY register operand.4 5# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=machine-scheduler \6# RUN: -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s7# REQUIRES: asserts8 9# CHECK: ScheduleDAGMI::schedule starting10# CHECK: SU(4): renamable $r2l = MSR renamable $r2l(tied-def 0), renamable $r2l11# CHECK: Latency : 612# CHECK: SU(5): renamable $r2l = MSY renamable $r2l(tied-def 0), renamable $r1d, -4, $noreg, implicit $r2d13# CHECK: Predecessors:14# CHECK: SU(4): Data Latency=2 Reg=$r2l15# CHECK: SU(4): Data Latency=0 Reg=$r2d16 17---18name: Perl_do_sv_dump19alignment: 1620tracksRegLiveness: true21body: |22 bb.0 :23 %1:addr64bit = IMPLICIT_DEF24 %2:addr64bit = IMPLICIT_DEF25 %3:vr64bit = IMPLICIT_DEF26 27 bb.1 :28 %2:addr64bit = ALGFI %2, 4294967291, implicit-def dead $cc29 %2.subreg_l32:addr64bit = MSR %2.subreg_l32, %2.subreg_l3230 %2.subreg_l32:addr64bit = MSY %2.subreg_l32, %1, -4, $noreg31...32