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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit OR in vector registers on z133;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; Or.7define i128 @f1(i128 %a, i128 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r4), 311; CHECK-NEXT: vl %v1, 0(%r3), 312; CHECK-NEXT: vo %v0, %v1, %v013; CHECK-NEXT: vst %v0, 0(%r2), 314; CHECK-NEXT: br %r1415 %res = or i128 %a, %b16 ret i128 %res17}18 19; NOR.20define i128 @f2(i128 %a, i128 %b) {21; CHECK-LABEL: f2:22; CHECK: # %bb.0:23; CHECK-NEXT: vl %v0, 0(%r4), 324; CHECK-NEXT: vl %v1, 0(%r3), 325; CHECK-NEXT: vno %v0, %v1, %v026; CHECK-NEXT: vst %v0, 0(%r2), 327; CHECK-NEXT: br %r1428 %op = or i128 %a, %b29 %res = xor i128 %op, -130 ret i128 %res31}32 33; Complement.34define i128 @f3(i128 %a) {35; CHECK-LABEL: f3:36; CHECK: # %bb.0:37; CHECK-NEXT: vl %v0, 0(%r3), 338; CHECK-NEXT: vno %v0, %v0, %v039; CHECK-NEXT: vst %v0, 0(%r2), 340; CHECK-NEXT: br %r1441 %res = xor i128 %a, -142 ret i128 %res43}44 45; Select.46define i128 @f4(i128 %mask, i128 %true, i128 %false) {47; CHECK-LABEL: f4:48; CHECK: # %bb.0:49; CHECK-NEXT: vl %v0, 0(%r3), 350; CHECK-NEXT: vl %v1, 0(%r5), 351; CHECK-NEXT: vl %v2, 0(%r4), 352; CHECK-NEXT: vsel %v0, %v2, %v1, %v053; CHECK-NEXT: vst %v0, 0(%r2), 354; CHECK-NEXT: br %r1455 %notmask = xor i128 %mask, -156 %res1 = and i128 %true, %mask57 %res2 = and i128 %false, %notmask58 %res = or i128 %res1, %res259 ret i128 %res60}61