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1# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=postmisched \2# RUN: -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s3# REQUIRES: asserts4 5# Test that the cycle index is the same before and after scheduling an6# instruction with 6 decoder slots.7 8# CHECK: ++ | Current cycle index: 39# CHECK-NEXT: ++ | Resource counters: Z13_FXaUnit:210# CHECK-NEXT: ** ScheduleDAGMI::schedule picking next node11# CHECK-NEXT: ** Available: {SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone, SU(6):LARL/FXa}12# CHECK-NEXT: ** Best so far: SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone Grouping cost:-1 Height:4313# CHECK-NEXT: ** Tried : SU(6):LARL/FXa Height:1414# CHECK-NEXT: ** Scheduling SU(3) Grouping cost:-115# CHECK-NEXT: ++ HazardRecognizer emitting SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone16# CHECK-NEXT: ++ Decode group before emission: <empty>17# CHECK-NEXT: ++ Completed decode group: { SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone } (6 decoder slots)18# CHECK-NEXT: ++ | Current decoder group: <empty>19# CHECK-NEXT: ++ | Current cycle index: 320 21 22--- |23 ; ModuleID = '<stdin>'24 source_filename = "<stdin>"25 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"26 target triple = "s390x--linux-gnu"27 28 %0 = type { i8, i8, i8, i8, i16, i32, i32, i32 }29 30 @TTSize = external dso_local local_unnamed_addr global i32, align 431 @AS_TTable = external dso_local local_unnamed_addr global ptr, align 832 @Variant = external dso_local local_unnamed_addr global i32, align 433 34 define dso_local void @LearnStoreTT(i32 signext %arg, i32 zeroext %arg1, i32 signext %arg2) #0 {35 bb:36 %tmp = load i32, ptr @TTSize, align 437 %tmp3 = urem i32 %arg1, %tmp38 %tmp4 = load ptr, ptr @AS_TTable, align 839 %tmp5 = zext i32 %tmp3 to i6440 %tmp6 = load i32, ptr @Variant, align 441 %tmp7 = add i32 %tmp6, -342 %tmp8 = icmp ugt i32 %tmp7, 143 %tmp9 = select i1 %tmp8, i8 3, i8 144 store i8 %tmp9, ptr undef, align 145 store i32 %arg, ptr undef, align 446 %tmp10 = trunc i32 %arg2 to i847 store i8 %tmp10, ptr null, align 148 %tmp11 = getelementptr inbounds %0, ptr %tmp4, i64 %tmp5, i32 249 store i8 0, ptr %tmp11, align 250 ret void51 }52 53 attributes #0 = { "target-cpu"="z13" }54 55...56---57name: LearnStoreTT58alignment: 1659tracksRegLiveness: true60liveins: 61 - { reg: '$r2d' }62 - { reg: '$r3d' }63 - { reg: '$r4d' }64frameInfo: 65 maxCallFrameSize: 066body: |67 bb.0.bb:68 liveins: $r2d, $r3d, $r4d69 70 $r1d = LGR $r3d, implicit-def $r0q71 renamable $r3d = LARL @TTSize72 renamable $r0d = LLILL 0, implicit killed $r0q, implicit-def $r0q73 renamable $r0q = DL killed renamable $r0q, killed renamable $r3d, 0, $noreg :: (dereferenceable load (s32) from @TTSize)74 renamable $r3d = LGRL @AS_TTable :: (dereferenceable load (s64) from @AS_TTable)75 renamable $r1d = LLGFR renamable $r0l, implicit killed $r0q76 renamable $r5d = LARL @Variant77 renamable $r0l = LHI -378 renamable $r0l = A killed renamable $r0l, killed renamable $r5d, 0, $noreg, implicit-def dead $cc :: (dereferenceable load (s32) from @Variant)79 CLFI killed renamable $r0l, 1, implicit-def $cc80 renamable $r0l = LHI 181 renamable $r0l = LOCHI killed renamable $r0l, 3, 14, 2, implicit killed $cc82 STC killed renamable $r0l, undef renamable $r1d, 0, $noreg :: (store (s8) into `ptr undef`)83 ST renamable $r2l, undef renamable $r1d, 0, $noreg, implicit killed $r2d :: (store (s32) into `ptr undef`)84 STC renamable $r4l, $noreg, 0, $noreg, implicit killed $r4d :: (store (s8) into `ptr null`)85 renamable $r1d = MGHI killed renamable $r1d, 2086 renamable $r0l = LHI 087 STC killed renamable $r0l, killed renamable $r3d, 2, killed renamable $r1d :: (store (s8) into %ir.tmp11, align 2)88 Return89 90...91