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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Test sequences that can use RISBG with a zeroed first operand.3; The tests here assume that RISBLG isn't available.4;5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s6 7; Test an extraction of bit 0 from a right-shifted value.8define i32 @f1(i32 %foo) {9; CHECK-LABEL: f1:10; CHECK: # %bb.0:11; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d12; CHECK-NEXT: risbg %r2, %r2, 63, 191, 5413; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d14; CHECK-NEXT: br %r1415 %shr = lshr i32 %foo, 1016 %and = and i32 %shr, 117 ret i32 %and18}19 20; ...and again with i64.21define i64 @f2(i64 %foo) {22; CHECK-LABEL: f2:23; CHECK: # %bb.0:24; CHECK-NEXT: risbg %r2, %r2, 63, 191, 5425; CHECK-NEXT: br %r1426 %shr = lshr i64 %foo, 1027 %and = and i64 %shr, 128 ret i64 %and29}30 31; Test an extraction of other bits from a right-shifted value.32define i32 @f3(i32 %foo) {33; CHECK-LABEL: f3:34; CHECK: # %bb.0:35; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d36; CHECK-NEXT: risbg %r2, %r2, 60, 189, 4237; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d38; CHECK-NEXT: br %r1439 %shr = lshr i32 %foo, 2240 %and = and i32 %shr, 1241 ret i32 %and42}43 44; ...and again with i64.45define i64 @f4(i64 %foo) {46; CHECK-LABEL: f4:47; CHECK: # %bb.0:48; CHECK-NEXT: risbg %r2, %r2, 60, 189, 4249; CHECK-NEXT: br %r1450 %shr = lshr i64 %foo, 2251 %and = and i64 %shr, 1252 ret i64 %and53}54 55; Test an extraction of most bits from a right-shifted value.56; The range should be reduced to exclude the zeroed high bits.57define i32 @f5(i32 %foo) {58; CHECK-LABEL: f5:59; CHECK: # %bb.0:60; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d61; CHECK-NEXT: risbg %r2, %r2, 34, 188, 6262; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d63; CHECK-NEXT: br %r1464 %shr = lshr i32 %foo, 265 %and = and i32 %shr, -866 ret i32 %and67}68 69; ...and again with i64.70define i64 @f6(i64 %foo) {71; CHECK-LABEL: f6:72; CHECK: # %bb.0:73; CHECK-NEXT: risbg %r2, %r2, 2, 188, 6274; CHECK-NEXT: br %r1475 %shr = lshr i64 %foo, 276 %and = and i64 %shr, -877 ret i64 %and78}79 80; Try the next value up (mask ....1111001). This needs a separate shift81; and mask.82define i32 @f7(i32 %foo) {83; CHECK-LABEL: f7:84; CHECK: # %bb.0:85; CHECK-NEXT: srl %r2, 286; CHECK-NEXT: nill %r2, 6552987; CHECK-NEXT: br %r1488 %shr = lshr i32 %foo, 289 %and = and i32 %shr, -790 ret i32 %and91}92 93; ...and again with i64.94define i64 @f8(i64 %foo) {95; CHECK-LABEL: f8:96; CHECK: # %bb.0:97; CHECK-NEXT: srlg %r2, %r2, 298; CHECK-NEXT: nill %r2, 6552999; CHECK-NEXT: br %r14100 %shr = lshr i64 %foo, 2101 %and = and i64 %shr, -7102 ret i64 %and103}104 105; Test an extraction of bits from a left-shifted value. The range should106; be reduced to exclude the zeroed low bits.107define i32 @f9(i32 %foo) {108; CHECK-LABEL: f9:109; CHECK: # %bb.0:110; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d111; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2112; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d113; CHECK-NEXT: br %r14114 %shr = shl i32 %foo, 2115 %and = and i32 %shr, 255116 ret i32 %and117}118 119; ...and again with i64.120define i64 @f10(i64 %foo) {121; CHECK-LABEL: f10:122; CHECK: # %bb.0:123; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2124; CHECK-NEXT: br %r14125 %shr = shl i64 %foo, 2126 %and = and i64 %shr, 255127 ret i64 %and128}129 130; Try a wrap-around mask (mask ....111100001111). This needs a separate shift131; and mask.132define i32 @f11(i32 %foo) {133; CHECK-LABEL: f11:134; CHECK: # %bb.0:135; CHECK-NEXT: sll %r2, 2136; CHECK-NEXT: nill %r2, 65295137; CHECK-NEXT: br %r14138 %shr = shl i32 %foo, 2139 %and = and i32 %shr, -241140 ret i32 %and141}142 143; ...and again with i64.144define i64 @f12(i64 %foo) {145; CHECK-LABEL: f12:146; CHECK: # %bb.0:147; CHECK-NEXT: sllg %r2, %r2, 2148; CHECK-NEXT: nill %r2, 65295149; CHECK-NEXT: br %r14150 %shr = shl i64 %foo, 2151 %and = and i64 %shr, -241152 ret i64 %and153}154 155; Test an extraction from a rotated value, no mask wraparound.156; This is equivalent to the lshr case, because the bits from the157; shl are not used.158define i32 @f13(i32 %foo) {159; CHECK-LABEL: f13:160; CHECK: # %bb.0:161; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d162; CHECK-NEXT: risbg %r2, %r2, 56, 188, 46163; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d164; CHECK-NEXT: br %r14165 %parta = shl i32 %foo, 14166 %partb = lshr i32 %foo, 18167 %rotl = or i32 %parta, %partb168 %and = and i32 %rotl, 248169 ret i32 %and170}171 172; ...and again with i64.173define i64 @f14(i64 %foo) {174; CHECK-LABEL: f14:175; CHECK: # %bb.0:176; CHECK-NEXT: risbg %r2, %r2, 56, 188, 14177; CHECK-NEXT: br %r14178 %parta = shl i64 %foo, 14179 %partb = lshr i64 %foo, 50180 %rotl = or i64 %parta, %partb181 %and = and i64 %rotl, 248182 ret i64 %and183}184 185; Try a case in which only the bits from the shl are used.186define i32 @f15(i32 %foo) {187; CHECK-LABEL: f15:188; CHECK: # %bb.0:189; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d190; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14191; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d192; CHECK-NEXT: br %r14193 %parta = shl i32 %foo, 14194 %partb = lshr i32 %foo, 18195 %rotl = or i32 %parta, %partb196 %and = and i32 %rotl, 114688197 ret i32 %and198}199 200; ...and again with i64.201define i64 @f16(i64 %foo) {202; CHECK-LABEL: f16:203; CHECK: # %bb.0:204; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14205; CHECK-NEXT: br %r14206 %parta = shl i64 %foo, 14207 %partb = lshr i64 %foo, 50208 %rotl = or i64 %parta, %partb209 %and = and i64 %rotl, 114688210 ret i64 %and211}212 213; Test a 32-bit rotate in which both parts of the OR are needed.214; This needs a separate shift and mask.215define i32 @f17(i32 %foo) {216; CHECK-LABEL: f17:217; CHECK: # %bb.0:218; CHECK-NEXT: rll %r2, %r2, 4219; CHECK-NEXT: nilf %r2, 126220; CHECK-NEXT: br %r14221 %parta = shl i32 %foo, 4222 %partb = lshr i32 %foo, 28223 %rotl = or i32 %parta, %partb224 %and = and i32 %rotl, 126225 ret i32 %and226}227 228; ...and for i64, where RISBG should do the rotate too.229define i64 @f18(i64 %foo) {230; CHECK-LABEL: f18:231; CHECK: # %bb.0:232; CHECK-NEXT: risbg %r2, %r2, 57, 190, 4233; CHECK-NEXT: br %r14234 %parta = shl i64 %foo, 4235 %partb = lshr i64 %foo, 60236 %rotl = or i64 %parta, %partb237 %and = and i64 %rotl, 126238 ret i64 %and239}240 241; Test an arithmetic shift right in which some of the sign bits are kept.242; This needs a separate shift and mask.243define i32 @f19(i32 %foo) {244; CHECK-LABEL: f19:245; CHECK: # %bb.0:246; CHECK-NEXT: sra %r2, 28247; CHECK-NEXT: nilf %r2, 30248; CHECK-NEXT: br %r14249 %shr = ashr i32 %foo, 28250 %and = and i32 %shr, 30251 ret i32 %and252}253 254; ...and again with i64. In this case RISBG is the best way of doing the AND.255define i64 @f20(i64 %foo) {256; CHECK-LABEL: f20:257; CHECK: # %bb.0:258; CHECK-NEXT: srag %r0, %r2, 60259; CHECK-NEXT: risbg %r2, %r0, 59, 190, 0260; CHECK-NEXT: br %r14261 %shr = ashr i64 %foo, 60262 %and = and i64 %shr, 30263 ret i64 %and264}265 266; Now try an arithmetic right shift in which the sign bits aren't needed.267; Introduce a second use of %shr so that the ashr doesn't decompose to268; an lshr.269; NOTE: the extra move to %r2 should not be needed (temporary FAIL)270define i32 @f21(i32 %foo, ptr %dest) {271; CHECK-LABEL: f21:272; CHECK: # %bb.0:273; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d274; CHECK-NEXT: risbg %r0, %r2, 60, 190, 36275; CHECK-NEXT: lr %r1, %r2276; CHECK-NEXT: sra %r1, 28277; CHECK-NEXT: st %r1, 0(%r3)278; CHECK-NEXT: lr %r2, %r0279; CHECK-NEXT: br %r14280 %shr = ashr i32 %foo, 28281 store i32 %shr, ptr %dest282 %and = and i32 %shr, 14283 ret i32 %and284}285 286; ...and again with i64.287define i64 @f22(i64 %foo, ptr %dest) {288; CHECK-LABEL: f22:289; CHECK: # %bb.0:290; CHECK-NEXT: srag %r0, %r2, 60291; CHECK-NEXT: risbg %r2, %r2, 60, 190, 4292; CHECK-NEXT: stg %r0, 0(%r3)293; CHECK-NEXT: br %r14294 %shr = ashr i64 %foo, 60295 store i64 %shr, ptr %dest296 %and = and i64 %shr, 14297 ret i64 %and298}299 300; Check that we use RISBG for shifted values even if the AND is a301; natural zero extension.302define i64 @f23(i64 %foo) {303; CHECK-LABEL: f23:304; CHECK: # %bb.0:305; CHECK-NEXT: risbg %r2, %r2, 56, 191, 62306; CHECK-NEXT: br %r14307 %shr = lshr i64 %foo, 2308 %and = and i64 %shr, 255309 ret i64 %and310}311 312; Test a case where the AND comes before a rotate. This needs a separate313; mask and rotate.314define i32 @f24(i32 %foo) {315; CHECK-LABEL: f24:316; CHECK: # %bb.0:317; CHECK-NEXT: nilf %r2, 254318; CHECK-NEXT: rll %r2, %r2, 29319; CHECK-NEXT: br %r14320 %and = and i32 %foo, 254321 %parta = lshr i32 %and, 3322 %partb = shl i32 %and, 29323 %rotl = or i32 %parta, %partb324 ret i32 %rotl325}326 327; ...and again with i64, where a single RISBG is enough.328define i64 @f25(i64 %foo) {329; CHECK-LABEL: f25:330; CHECK: # %bb.0:331; CHECK-NEXT: risbg %r2, %r2, 57, 187, 3332; CHECK-NEXT: br %r14333 %and = and i64 %foo, 14334 %parta = shl i64 %and, 3335 %partb = lshr i64 %and, 61336 %rotl = or i64 %parta, %partb337 ret i64 %rotl338}339 340; Test a wrap-around case in which the AND comes before a rotate.341; This again needs a separate mask and rotate.342define i32 @f26(i32 %foo) {343; CHECK-LABEL: f26:344; CHECK: # %bb.0:345; CHECK-NEXT: nill %r2, 65487346; CHECK-NEXT: rll %r2, %r2, 5347; CHECK-NEXT: br %r14348 %and = and i32 %foo, -49349 %parta = shl i32 %and, 5350 %partb = lshr i32 %and, 27351 %rotl = or i32 %parta, %partb352 ret i32 %rotl353}354 355; ...and again with i64, where a single RISBG is OK.356define i64 @f27(i64 %foo) {357; CHECK-LABEL: f27:358; CHECK: # %bb.0:359; CHECK-NEXT: risbg %r2, %r2, 55, 180, 5360; CHECK-NEXT: br %r14361 %and = and i64 %foo, -49362 %parta = shl i64 %and, 5363 %partb = lshr i64 %and, 59364 %rotl = or i64 %parta, %partb365 ret i64 %rotl366}367 368; Test a case where the AND comes before a shift left.369define i32 @f28(i32 %foo) {370; CHECK-LABEL: f28:371; CHECK: # %bb.0:372; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d373; CHECK-NEXT: risbg %r2, %r2, 32, 173, 17374; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d375; CHECK-NEXT: br %r14376 %and = and i32 %foo, 32766377 %shl = shl i32 %and, 17378 ret i32 %shl379}380 381; ...and again with i64.382define i64 @f29(i64 %foo) {383; CHECK-LABEL: f29:384; CHECK: # %bb.0:385; CHECK-NEXT: risbg %r2, %r2, 0, 141, 49386; CHECK-NEXT: br %r14387 %and = and i64 %foo, 32766388 %shl = shl i64 %and, 49389 ret i64 %shl390}391 392; Test the next shift up from f28, in which the mask should get shortened.393define i32 @f30(i32 %foo) {394; CHECK-LABEL: f30:395; CHECK: # %bb.0:396; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d397; CHECK-NEXT: risbg %r2, %r2, 32, 172, 18398; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d399; CHECK-NEXT: br %r14400 %and = and i32 %foo, 32766401 %shl = shl i32 %and, 18402 ret i32 %shl403}404 405; ...and again with i64.406define i64 @f31(i64 %foo) {407; CHECK-LABEL: f31:408; CHECK: # %bb.0:409; CHECK-NEXT: risbg %r2, %r2, 0, 140, 50410; CHECK-NEXT: br %r14411 %and = and i64 %foo, 32766412 %shl = shl i64 %and, 50413 ret i64 %shl414}415 416; Test a wrap-around case in which the shift left comes after the AND.417; We can't use RISBG for the shift in that case.418define i32 @f32(i32 %foo) {419; CHECK-LABEL: f32:420; CHECK: # %bb.0:421; CHECK-NEXT: nilf %r2, 4194297422; CHECK-NEXT: sll %r2, 10423; CHECK-NEXT: br %r14424 %and = and i32 %foo, -7425 %shl = shl i32 %and, 10426 ret i32 %shl427}428 429; ...and again with i64.430define i64 @f33(i64 %foo) {431; CHECK-LABEL: f33:432; CHECK: # %bb.0:433; CHECK-NEXT: llihf %r0, 4194303434; CHECK-NEXT: oilf %r0, 4294967289435; CHECK-NEXT: ngr %r0, %r2436; CHECK-NEXT: sllg %r2, %r0, 10437; CHECK-NEXT: br %r14438 %and = and i64 %foo, -7439 %shl = shl i64 %and, 10440 ret i64 %shl441}442 443; Test a case where the AND comes before a shift right.444define i32 @f34(i32 %foo) {445; CHECK-LABEL: f34:446; CHECK: # %bb.0:447; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d448; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55449; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d450; CHECK-NEXT: br %r14451 %and = and i32 %foo, 65535452 %shl = lshr i32 %and, 9453 ret i32 %shl454}455 456; ...and again with i64.457define i64 @f35(i64 %foo) {458; CHECK-LABEL: f35:459; CHECK: # %bb.0:460; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55461; CHECK-NEXT: br %r14462 %and = and i64 %foo, 65535463 %shl = lshr i64 %and, 9464 ret i64 %shl465}466 467; Test a wrap-around case where the AND comes before a shift right.468; We can't use RISBG for the shift in that case.469define i32 @f36(i32 %foo) {470; CHECK-LABEL: f36:471; CHECK: # %bb.0:472; CHECK-NEXT: nill %r2, 65510473; CHECK-NEXT: srl %r2, 1474; CHECK-NEXT: br %r14475 %and = and i32 %foo, -25476 %shl = lshr i32 %and, 1477 ret i32 %shl478}479 480; ...and again with i64.481define i64 @f37(i64 %foo) {482; CHECK-LABEL: f37:483; CHECK: # %bb.0:484; CHECK-NEXT: nill %r2, 65510485; CHECK-NEXT: srlg %r2, %r2, 1486; CHECK-NEXT: br %r14487 %and = and i64 %foo, -25488 %shl = lshr i64 %and, 1489 ret i64 %shl490}491 492; Test a combination involving a large ASHR and a shift left. We can't493; use RISBG there.494define i64 @f38(i64 %foo) {495; CHECK-LABEL: f38:496; CHECK: # %bb.0:497; CHECK-NEXT: srag %r0, %r2, 32498; CHECK-NEXT: sllg %r2, %r0, 5499; CHECK-NEXT: br %r14500 %ashr = ashr i64 %foo, 32501 %shl = shl i64 %ashr, 5502 ret i64 %shl503}504 505; Try a similar thing in which no shifted sign bits are kept.506define i64 @f39(i64 %foo, ptr %dest) {507; CHECK-LABEL: f39:508; CHECK: # %bb.0:509; CHECK-NEXT: srag %r0, %r2, 35510; CHECK-NEXT: risbg %r2, %r2, 33, 189, 31511; CHECK-NEXT: stg %r0, 0(%r3)512; CHECK-NEXT: br %r14513 %ashr = ashr i64 %foo, 35514 store i64 %ashr, ptr %dest515 %shl = shl i64 %ashr, 2516 %and = and i64 %shl, 2147483647517 ret i64 %and518}519 520; ...and again with the next highest shift value, where one sign bit is kept.521define i64 @f40(i64 %foo, ptr %dest) {522; CHECK-LABEL: f40:523; CHECK: # %bb.0:524; CHECK-NEXT: srag %r0, %r2, 36525; CHECK-NEXT: risbg %r2, %r0, 33, 189, 2526; CHECK-NEXT: stg %r0, 0(%r3)527; CHECK-NEXT: br %r14528 %ashr = ashr i64 %foo, 36529 store i64 %ashr, ptr %dest530 %shl = shl i64 %ashr, 2531 %and = and i64 %shl, 2147483647532 ret i64 %and533}534 535; Check a case where the result is zero-extended.536define i64 @f41(i32 %a) {537; CHECK-LABEL: f41:538; CHECK: # %bb.0:539; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d540; CHECK-NEXT: risbg %r2, %r2, 36, 191, 62541; CHECK-NEXT: br %r14542 %shl = shl i32 %a, 2543 %shr = lshr i32 %shl, 4544 %ext = zext i32 %shr to i64545 ret i64 %ext546}547 548; In this case the sign extension is converted to a pair of 32-bit shifts,549; which is then extended to 64 bits. We previously used the wrong bit size550; when testing whether the shifted-in bits of the shift right were significant.551define i64 @f42(i1 %x) {552; CHECK-LABEL: f42:553; CHECK: # %bb.0:554; CHECK-NEXT: nilf %r2, 1555; CHECK-NEXT: lcr %r0, %r2556; CHECK-NEXT: llgcr %r2, %r0557; CHECK-NEXT: br %r14558 %ext = sext i1 %x to i8559 %ext2 = zext i8 %ext to i64560 ret i64 %ext2561}562 563; Check that we get the case where a 64-bit shift is used by a 32-bit and.564define signext i32 @f43(i64 %x) {565; CHECK-LABEL: f43:566; CHECK: # %bb.0:567; CHECK-NEXT: risbg %r0, %r2, 32, 189, 52568; CHECK-NEXT: lgfr %r2, %r0569; CHECK-NEXT: br %r14570 %shr3 = lshr i64 %x, 12571 %shr3.tr = trunc i64 %shr3 to i32572 %conv = and i32 %shr3.tr, -4573 ret i32 %conv574}575 576; Check that we don't get the case where the 32-bit and mask is not contiguous577define signext i32 @f44(i64 %x) {578; CHECK-LABEL: f44:579; CHECK: # %bb.0:580; CHECK-NEXT: srlg %r0, %r2, 12581; CHECK-NEXT: lghi %r2, 10582; CHECK-NEXT: ngr %r2, %r0583; CHECK-NEXT: br %r14584 %shr4 = lshr i64 %x, 12585 %conv = trunc i64 %shr4 to i32586 %and = and i32 %conv, 10587 ret i32 %and588}589