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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Test sequences that can use RISBG with a normal first operand.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s5 6; Test a case with two ANDs.7define i32 @f1(i32 %a, i32 %b) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d11; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d12; CHECK-NEXT: risbg %r2, %r3, 60, 62, 013; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d14; CHECK-NEXT: br %r1415 %anda = and i32 %a, -1516 %andb = and i32 %b, 1417 %or = or i32 %anda, %andb18 ret i32 %or19}20 21; ...and again with i64.22define i64 @f2(i64 %a, i64 %b) {23; CHECK-LABEL: f2:24; CHECK: # %bb.0:25; CHECK-NEXT: risbg %r2, %r3, 60, 62, 026; CHECK-NEXT: br %r1427 %anda = and i64 %a, -1528 %andb = and i64 %b, 1429 %or = or i64 %anda, %andb30 ret i64 %or31}32 33; Test a case with two ANDs and a shift.34define i32 @f3(i32 %a, i32 %b) {35; CHECK-LABEL: f3:36; CHECK: # %bb.0:37; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d38; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d39; CHECK-NEXT: risbg %r2, %r3, 60, 63, 5640; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d41; CHECK-NEXT: br %r1442 %anda = and i32 %a, -1643 %shr = lshr i32 %b, 844 %andb = and i32 %shr, 1545 %or = or i32 %anda, %andb46 ret i32 %or47}48 49; ...and again with i64.50define i64 @f4(i64 %a, i64 %b) {51; CHECK-LABEL: f4:52; CHECK: # %bb.0:53; CHECK-NEXT: risbg %r2, %r3, 60, 63, 5654; CHECK-NEXT: br %r1455 %anda = and i64 %a, -1656 %shr = lshr i64 %b, 857 %andb = and i64 %shr, 1558 %or = or i64 %anda, %andb59 ret i64 %or60}61 62; Test a case with a single AND and a left shift.63define i32 @f5(i32 %a, i32 %b) {64; CHECK-LABEL: f5:65; CHECK: # %bb.0:66; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d67; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d68; CHECK-NEXT: risbg %r2, %r3, 32, 53, 1069; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d70; CHECK-NEXT: br %r1471 %anda = and i32 %a, 102372 %shlb = shl i32 %b, 1073 %or = or i32 %anda, %shlb74 ret i32 %or75}76 77; ...and again with i64.78define i64 @f6(i64 %a, i64 %b) {79; CHECK-LABEL: f6:80; CHECK: # %bb.0:81; CHECK-NEXT: risbg %r2, %r3, 0, 53, 1082; CHECK-NEXT: br %r1483 %anda = and i64 %a, 102384 %shlb = shl i64 %b, 1085 %or = or i64 %anda, %shlb86 ret i64 %or87}88 89; Test a case with a single AND and a right shift.90define i32 @f7(i32 %a, i32 %b) {91; CHECK-LABEL: f7:92; CHECK: # %bb.0:93; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d94; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d95; CHECK-NEXT: risbg %r2, %r3, 40, 63, 5696; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d97; CHECK-NEXT: br %r1498 %anda = and i32 %a, -1677721699 %shrb = lshr i32 %b, 8100 %or = or i32 %anda, %shrb101 ret i32 %or102}103 104; ...and again with i64.105define i64 @f8(i64 %a, i64 %b) {106; CHECK-LABEL: f8:107; CHECK: # %bb.0:108; CHECK-NEXT: risbg %r2, %r3, 8, 63, 56109; CHECK-NEXT: br %r14110 %anda = and i64 %a, -72057594037927936111 %shrb = lshr i64 %b, 8112 %or = or i64 %anda, %shrb113 ret i64 %or114}115 116; Check that we can get the case where a 64-bit shift feeds a 32-bit or of117; ands with complement masks.118define signext i32 @f9(i64 %x, i32 signext %y) {119; CHECK-LABEL: f9:120; CHECK: # %bb.0:121; CHECK-NEXT: risbg %r3, %r2, 48, 63, 16122; CHECK-NEXT: lgfr %r2, %r3123; CHECK-NEXT: br %r14124 %shr6 = lshr i64 %x, 48125 %conv = trunc i64 %shr6 to i32126 %and1 = and i32 %y, -65536127 %or = or i32 %conv, %and1128 ret i32 %or129}130 131; Check that we don't get the case where a 64-bit shift feeds a 32-bit or of132; ands with incompatible masks.133define signext i32 @f10(i64 %x, i32 signext %y) {134; CHECK-LABEL: f10:135; CHECK: # %bb.0:136; CHECK-NEXT: nilf %r3, 4278190080137; CHECK-NEXT: rosbg %r3, %r2, 48, 63, 16138; CHECK-NEXT: lgfr %r2, %r3139; CHECK-NEXT: br %r14140 %shr6 = lshr i64 %x, 48141 %conv = trunc i64 %shr6 to i32142 %and1 = and i32 %y, -16777216143 %or = or i32 %conv, %and1144 ret i32 %or145}146