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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Test sequences that can use RISBG with a zeroed first operand.3; The tests here assume that RISBLG is available.4;5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s6 7; Test an extraction of bit 0 from a right-shifted value.8define i32 @f1(i32 %foo) {9; CHECK-LABEL: f1:10; CHECK: # %bb.0:11; CHECK-NEXT: risblg %r2, %r2, 31, 159, 5412; CHECK-NEXT: br %r1413 %shr = lshr i32 %foo, 1014 %and = and i32 %shr, 115 ret i32 %and16}17 18; ...and again with i64.19define i64 @f2(i64 %foo) {20; CHECK-LABEL: f2:21; CHECK: # %bb.0:22; CHECK-NEXT: risbg %r2, %r2, 63, 191, 5423; CHECK-NEXT: br %r1424 %shr = lshr i64 %foo, 1025 %and = and i64 %shr, 126 ret i64 %and27}28 29; Test an extraction of other bits from a right-shifted value.30define i32 @f3(i32 %foo) {31; CHECK-LABEL: f3:32; CHECK: # %bb.0:33; CHECK-NEXT: risblg %r2, %r2, 28, 157, 4234; CHECK-NEXT: br %r1435 %shr = lshr i32 %foo, 2236 %and = and i32 %shr, 1237 ret i32 %and38}39 40; ...and again with i64.41define i64 @f4(i64 %foo) {42; CHECK-LABEL: f4:43; CHECK: # %bb.0:44; CHECK-NEXT: risbg %r2, %r2, 60, 189, 4245; CHECK-NEXT: br %r1446 %shr = lshr i64 %foo, 2247 %and = and i64 %shr, 1248 ret i64 %and49}50 51; Test an extraction of most bits from a right-shifted value.52; The range should be reduced to exclude the zeroed high bits.53define i32 @f5(i32 %foo) {54; CHECK-LABEL: f5:55; CHECK: # %bb.0:56; CHECK-NEXT: risblg %r2, %r2, 2, 156, 6257; CHECK-NEXT: br %r1458 %shr = lshr i32 %foo, 259 %and = and i32 %shr, -860 ret i32 %and61}62 63; ...and again with i64.64define i64 @f6(i64 %foo) {65; CHECK-LABEL: f6:66; CHECK: # %bb.0:67; CHECK-NEXT: risbg %r2, %r2, 2, 188, 6268; CHECK-NEXT: br %r1469 %shr = lshr i64 %foo, 270 %and = and i64 %shr, -871 ret i64 %and72}73 74; Try the next value up (mask ....1111001). This needs a separate shift75; and mask.76define i32 @f7(i32 %foo) {77; CHECK-LABEL: f7:78; CHECK: # %bb.0:79; CHECK-NEXT: srl %r2, 280; CHECK-NEXT: nill %r2, 6552981; CHECK-NEXT: br %r1482 %shr = lshr i32 %foo, 283 %and = and i32 %shr, -784 ret i32 %and85}86 87; ...and again with i64.88define i64 @f8(i64 %foo) {89; CHECK-LABEL: f8:90; CHECK: # %bb.0:91; CHECK-NEXT: srlg %r2, %r2, 292; CHECK-NEXT: nill %r2, 6552993; CHECK-NEXT: br %r1494 %shr = lshr i64 %foo, 295 %and = and i64 %shr, -796 ret i64 %and97}98 99; Test an extraction of bits from a left-shifted value. The range should100; be reduced to exclude the zeroed low bits.101define i32 @f9(i32 %foo) {102; CHECK-LABEL: f9:103; CHECK: # %bb.0:104; CHECK-NEXT: risblg %r2, %r2, 24, 157, 2105; CHECK-NEXT: br %r14106 %shr = shl i32 %foo, 2107 %and = and i32 %shr, 255108 ret i32 %and109}110 111; ...and again with i64.112define i64 @f10(i64 %foo) {113; CHECK-LABEL: f10:114; CHECK: # %bb.0:115; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2116; CHECK-NEXT: br %r14117 %shr = shl i64 %foo, 2118 %and = and i64 %shr, 255119 ret i64 %and120}121 122; Try a wrap-around mask (mask ....111100001111). This needs a separate shift123; and mask.124define i32 @f11(i32 %foo) {125; CHECK-LABEL: f11:126; CHECK: # %bb.0:127; CHECK-NEXT: sll %r2, 2128; CHECK-NEXT: nill %r2, 65295129; CHECK-NEXT: br %r14130 %shr = shl i32 %foo, 2131 %and = and i32 %shr, -241132 ret i32 %and133}134 135; ...and again with i64.136define i64 @f12(i64 %foo) {137; CHECK-LABEL: f12:138; CHECK: # %bb.0:139; CHECK-NEXT: sllg %r2, %r2, 2140; CHECK-NEXT: nill %r2, 65295141; CHECK-NEXT: br %r14142 %shr = shl i64 %foo, 2143 %and = and i64 %shr, -241144 ret i64 %and145}146 147; Test an extraction from a rotated value, no mask wraparound.148; This is equivalent to the lshr case, because the bits from the149; shl are not used.150define i32 @f13(i32 %foo) {151; CHECK-LABEL: f13:152; CHECK: # %bb.0:153; CHECK-NEXT: risblg %r2, %r2, 24, 156, 46154; CHECK-NEXT: br %r14155 %parta = shl i32 %foo, 14156 %partb = lshr i32 %foo, 18157 %rotl = or i32 %parta, %partb158 %and = and i32 %rotl, 248159 ret i32 %and160}161 162; ...and again with i64.163define i64 @f14(i64 %foo) {164; CHECK-LABEL: f14:165; CHECK: # %bb.0:166; CHECK-NEXT: risbg %r2, %r2, 56, 188, 14167; CHECK-NEXT: br %r14168 %parta = shl i64 %foo, 14169 %partb = lshr i64 %foo, 50170 %rotl = or i64 %parta, %partb171 %and = and i64 %rotl, 248172 ret i64 %and173}174 175; Try a case in which only the bits from the shl are used.176define i32 @f15(i32 %foo) {177; CHECK-LABEL: f15:178; CHECK: # %bb.0:179; CHECK-NEXT: risblg %r2, %r2, 15, 145, 14180; CHECK-NEXT: br %r14181 %parta = shl i32 %foo, 14182 %partb = lshr i32 %foo, 18183 %rotl = or i32 %parta, %partb184 %and = and i32 %rotl, 114688185 ret i32 %and186}187 188; ...and again with i64.189define i64 @f16(i64 %foo) {190; CHECK-LABEL: f16:191; CHECK: # %bb.0:192; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14193; CHECK-NEXT: br %r14194 %parta = shl i64 %foo, 14195 %partb = lshr i64 %foo, 50196 %rotl = or i64 %parta, %partb197 %and = and i64 %rotl, 114688198 ret i64 %and199}200 201; Test a 32-bit rotate in which both parts of the OR are needed.202; This needs a separate shift and mask.203define i32 @f17(i32 %foo) {204; CHECK-LABEL: f17:205; CHECK: # %bb.0:206; CHECK-NEXT: rll %r2, %r2, 4207; CHECK-NEXT: nilf %r2, 126208; CHECK-NEXT: br %r14209 %parta = shl i32 %foo, 4210 %partb = lshr i32 %foo, 28211 %rotl = or i32 %parta, %partb212 %and = and i32 %rotl, 126213 ret i32 %and214}215 216; ...and for i64, where RISBG should do the rotate too.217define i64 @f18(i64 %foo) {218; CHECK-LABEL: f18:219; CHECK: # %bb.0:220; CHECK-NEXT: risbg %r2, %r2, 57, 190, 4221; CHECK-NEXT: br %r14222 %parta = shl i64 %foo, 4223 %partb = lshr i64 %foo, 60224 %rotl = or i64 %parta, %partb225 %and = and i64 %rotl, 126226 ret i64 %and227}228 229; Test an arithmetic shift right in which some of the sign bits are kept.230; This needs a separate shift and mask.231define i32 @f19(i32 %foo) {232; CHECK-LABEL: f19:233; CHECK: # %bb.0:234; CHECK-NEXT: sra %r2, 28235; CHECK-NEXT: nilf %r2, 30236; CHECK-NEXT: br %r14237 %shr = ashr i32 %foo, 28238 %and = and i32 %shr, 30239 ret i32 %and240}241 242; ...and again with i64. In this case RISBG is the best way of doing the AND.243define i64 @f20(i64 %foo) {244; CHECK-LABEL: f20:245; CHECK: # %bb.0:246; CHECK-NEXT: srag %r0, %r2, 60247; CHECK-NEXT: risbg %r2, %r0, 59, 190, 0248; CHECK-NEXT: br %r14249 %shr = ashr i64 %foo, 60250 %and = and i64 %shr, 30251 ret i64 %and252}253 254; Now try an arithmetic right shift in which the sign bits aren't needed.255; Introduce a second use of %shr so that the ashr doesn't decompose to256; an lshr.257define i32 @f21(i32 %foo, ptr %dest) {258; CHECK-LABEL: f21:259; CHECK: # %bb.0:260; CHECK-NEXT: srak %r0, %r2, 28261; CHECK-NEXT: risblg %r2, %r2, 28, 158, 36262; CHECK-NEXT: st %r0, 0(%r3)263; CHECK-NEXT: br %r14264 %shr = ashr i32 %foo, 28265 store i32 %shr, ptr %dest266 %and = and i32 %shr, 14267 ret i32 %and268}269 270; ...and again with i64.271define i64 @f22(i64 %foo, ptr %dest) {272; CHECK-LABEL: f22:273; CHECK: # %bb.0:274; CHECK-NEXT: srag %r0, %r2, 60275; CHECK-NEXT: risbg %r2, %r2, 60, 190, 4276; CHECK-NEXT: stg %r0, 0(%r3)277; CHECK-NEXT: br %r14278 %shr = ashr i64 %foo, 60279 store i64 %shr, ptr %dest280 %and = and i64 %shr, 14281 ret i64 %and282}283 284; Check that we use RISBG for shifted values even if the AND is a285; natural zero extension.286define i64 @f23(i64 %foo) {287; CHECK-LABEL: f23:288; CHECK: # %bb.0:289; CHECK-NEXT: risbg %r2, %r2, 56, 191, 62290; CHECK-NEXT: br %r14291 %shr = lshr i64 %foo, 2292 %and = and i64 %shr, 255293 ret i64 %and294}295 296; Test a case where the AND comes before a rotate. This needs a separate297; mask and rotate.298define i32 @f24(i32 %foo) {299; CHECK-LABEL: f24:300; CHECK: # %bb.0:301; CHECK-NEXT: nilf %r2, 254302; CHECK-NEXT: rll %r2, %r2, 29303; CHECK-NEXT: br %r14304 %and = and i32 %foo, 254305 %parta = lshr i32 %and, 3306 %partb = shl i32 %and, 29307 %rotl = or i32 %parta, %partb308 ret i32 %rotl309}310 311; ...and again with i64, where a single RISBG is enough.312define i64 @f25(i64 %foo) {313; CHECK-LABEL: f25:314; CHECK: # %bb.0:315; CHECK-NEXT: risbg %r2, %r2, 57, 187, 3316; CHECK-NEXT: br %r14317 %and = and i64 %foo, 14318 %parta = shl i64 %and, 3319 %partb = lshr i64 %and, 61320 %rotl = or i64 %parta, %partb321 ret i64 %rotl322}323 324; Test a wrap-around case in which the AND comes before a rotate.325; This again needs a separate mask and rotate.326define i32 @f26(i32 %foo) {327; CHECK-LABEL: f26:328; CHECK: # %bb.0:329; CHECK-NEXT: nill %r2, 65487330; CHECK-NEXT: rll %r2, %r2, 5331; CHECK-NEXT: br %r14332 %and = and i32 %foo, -49333 %parta = shl i32 %and, 5334 %partb = lshr i32 %and, 27335 %rotl = or i32 %parta, %partb336 ret i32 %rotl337}338 339; ...and again with i64, where a single RISBG is OK.340define i64 @f27(i64 %foo) {341; CHECK-LABEL: f27:342; CHECK: # %bb.0:343; CHECK-NEXT: risbg %r2, %r2, 55, 180, 5344; CHECK-NEXT: br %r14345 %and = and i64 %foo, -49346 %parta = shl i64 %and, 5347 %partb = lshr i64 %and, 59348 %rotl = or i64 %parta, %partb349 ret i64 %rotl350}351 352; Test a case where the AND comes before a shift left.353define i32 @f28(i32 %foo) {354; CHECK-LABEL: f28:355; CHECK: # %bb.0:356; CHECK-NEXT: risblg %r2, %r2, 0, 141, 17357; CHECK-NEXT: br %r14358 %and = and i32 %foo, 32766359 %shl = shl i32 %and, 17360 ret i32 %shl361}362 363; ...and again with i64.364define i64 @f29(i64 %foo) {365; CHECK-LABEL: f29:366; CHECK: # %bb.0:367; CHECK-NEXT: risbg %r2, %r2, 0, 141, 49368; CHECK-NEXT: br %r14369 %and = and i64 %foo, 32766370 %shl = shl i64 %and, 49371 ret i64 %shl372}373 374; Test the next shift up from f28, in which the mask should get shortened.375define i32 @f30(i32 %foo) {376; CHECK-LABEL: f30:377; CHECK: # %bb.0:378; CHECK-NEXT: risblg %r2, %r2, 0, 140, 18379; CHECK-NEXT: br %r14380 %and = and i32 %foo, 32766381 %shl = shl i32 %and, 18382 ret i32 %shl383}384 385; ...and again with i64.386define i64 @f31(i64 %foo) {387; CHECK-LABEL: f31:388; CHECK: # %bb.0:389; CHECK-NEXT: risbg %r2, %r2, 0, 140, 50390; CHECK-NEXT: br %r14391 %and = and i64 %foo, 32766392 %shl = shl i64 %and, 50393 ret i64 %shl394}395 396; Test a wrap-around case in which the shift left comes after the AND.397; We can't use RISBG for the shift in that case.398define i32 @f32(i32 %foo) {399; CHECK-LABEL: f32:400; CHECK: # %bb.0:401; CHECK-NEXT: nilf %r2, 4194297402; CHECK-NEXT: sll %r2, 10403; CHECK-NEXT: br %r14404 %and = and i32 %foo, -7405 %shl = shl i32 %and, 10406 ret i32 %shl407}408 409; ...and again with i64.410define i64 @f33(i64 %foo) {411; CHECK-LABEL: f33:412; CHECK: # %bb.0:413; CHECK-NEXT: llihf %r0, 4194303414; CHECK-NEXT: oilf %r0, 4294967289415; CHECK-NEXT: ngr %r0, %r2416; CHECK-NEXT: sllg %r2, %r0, 10417; CHECK-NEXT: br %r14418 %and = and i64 %foo, -7419 %shl = shl i64 %and, 10420 ret i64 %shl421}422 423; Test a case where the AND comes before a shift right.424define i32 @f34(i32 %foo) {425; CHECK-LABEL: f34:426; CHECK: # %bb.0:427; CHECK-NEXT: risblg %r2, %r2, 25, 159, 55428; CHECK-NEXT: br %r14429 %and = and i32 %foo, 65535430 %shl = lshr i32 %and, 9431 ret i32 %shl432}433 434; ...and again with i64.435define i64 @f35(i64 %foo) {436; CHECK-LABEL: f35:437; CHECK: # %bb.0:438; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55439; CHECK-NEXT: br %r14440 %and = and i64 %foo, 65535441 %shl = lshr i64 %and, 9442 ret i64 %shl443}444 445; Test a wrap-around case where the AND comes before a shift right.446; We can't use RISBG for the shift in that case.447define i32 @f36(i32 %foo) {448; CHECK-LABEL: f36:449; CHECK: # %bb.0:450; CHECK-NEXT: nill %r2, 65510451; CHECK-NEXT: srl %r2, 1452; CHECK-NEXT: br %r14453 %and = and i32 %foo, -25454 %shl = lshr i32 %and, 1455 ret i32 %shl456}457 458; ...and again with i64.459define i64 @f37(i64 %foo) {460; CHECK-LABEL: f37:461; CHECK: # %bb.0:462; CHECK-NEXT: nill %r2, 65510463; CHECK-NEXT: srlg %r2, %r2, 1464; CHECK-NEXT: br %r14465 %and = and i64 %foo, -25466 %shl = lshr i64 %and, 1467 ret i64 %shl468}469 470; Test a combination involving a large ASHR and a shift left. We can't471; use RISBG there.472define i64 @f38(i64 %foo) {473; CHECK-LABEL: f38:474; CHECK: # %bb.0:475; CHECK-NEXT: srag %r0, %r2, 32476; CHECK-NEXT: sllg %r2, %r0, 5477; CHECK-NEXT: br %r14478 %ashr = ashr i64 %foo, 32479 %shl = shl i64 %ashr, 5480 ret i64 %shl481}482 483; Try a similar thing in which no shifted sign bits are kept.484define i64 @f39(i64 %foo, ptr %dest) {485; CHECK-LABEL: f39:486; CHECK: # %bb.0:487; CHECK-NEXT: srag %r0, %r2, 35488; CHECK-NEXT: risbg %r2, %r2, 33, 189, 31489; CHECK-NEXT: stg %r0, 0(%r3)490; CHECK-NEXT: br %r14491 %ashr = ashr i64 %foo, 35492 store i64 %ashr, ptr %dest493 %shl = shl i64 %ashr, 2494 %and = and i64 %shl, 2147483647495 ret i64 %and496}497 498; ...and again with the next highest shift value, where one sign bit is kept.499define i64 @f40(i64 %foo, ptr %dest) {500; CHECK-LABEL: f40:501; CHECK: # %bb.0:502; CHECK-NEXT: srag %r0, %r2, 36503; CHECK-NEXT: risbg %r2, %r0, 33, 189, 2504; CHECK-NEXT: stg %r0, 0(%r3)505; CHECK-NEXT: br %r14506 %ashr = ashr i64 %foo, 36507 store i64 %ashr, ptr %dest508 %shl = shl i64 %ashr, 2509 %and = and i64 %shl, 2147483647510 ret i64 %and511}512 513; Check a case where the result is zero-extended.514define i64 @f41(i32 %a) {515; CHECK-LABEL: f41:516; CHECK: # %bb.0:517; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d518; CHECK-NEXT: risbg %r2, %r2, 36, 191, 62519; CHECK-NEXT: br %r14520 %shl = shl i32 %a, 2521 %shr = lshr i32 %shl, 4522 %ext = zext i32 %shr to i64523 ret i64 %ext524}525 526; In this case the sign extension is converted to a pair of 32-bit shifts,527; which is then extended to 64 bits. We previously used the wrong bit size528; when testing whether the shifted-in bits of the shift right were significant.529define i64 @f42(i1 %x) {530; CHECK-LABEL: f42:531; CHECK: # %bb.0:532; CHECK-NEXT: nilf %r2, 1533; CHECK-NEXT: lcr %r0, %r2534; CHECK-NEXT: llgcr %r2, %r0535; CHECK-NEXT: br %r14536 %ext = sext i1 %x to i8537 %ext2 = zext i8 %ext to i64538 ret i64 %ext2539}540 541; Check that we get the case where a 64-bit shift is used by a 32-bit and.542; Note that this cannot use RISBLG, but should use RISBG.543define signext i32 @f43(i64 %x) {544; CHECK-LABEL: f43:545; CHECK: # %bb.0:546; CHECK-NEXT: risbg %r0, %r2, 32, 189, 52547; CHECK-NEXT: lgfr %r2, %r0548; CHECK-NEXT: br %r14549 %shr3 = lshr i64 %x, 12550 %shr3.tr = trunc i64 %shr3 to i32551 %conv = and i32 %shr3.tr, -4552 ret i32 %conv553}554 555; Check that we don't get the case where the 32-bit and mask is not contiguous556define signext i32 @f44(i64 %x) {557; CHECK-LABEL: f44:558; CHECK: # %bb.0:559; CHECK-NEXT: srlg %r2, %r2, 12560; CHECK-NEXT: lghi %r0, 10561; CHECK-NEXT: ngr %r2, %r0562; CHECK-NEXT: br %r14563 %shr4 = lshr i64 %x, 12564 %conv = trunc i64 %shr4 to i32565 %and = and i32 %conv, 10566 ret i32 %and567}568