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1; Test sequences that can use RNSBG.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5; Test a simple mask, which is a wrap-around case.6define i32 @f1(i32 %a, i32 %b) {7; CHECK-LABEL: f1:8; CHECK: rnsbg %r2, %r3, 59, 56, 09; CHECK: br %r1410 %orb = or i32 %b, 9611 %and = and i32 %a, %orb12 ret i32 %and13}14 15; ...and again with i64.16define i64 @f2(i64 %a, i64 %b) {17; CHECK-LABEL: f2:18; CHECK: rnsbg %r2, %r3, 59, 56, 019; CHECK: br %r1420 %orb = or i64 %b, 9621 %and = and i64 %a, %orb22 ret i64 %and23}24 25; Test a case where no wraparound is needed.26define i32 @f3(i32 %a, i32 %b) {27; CHECK-LABEL: f3:28; CHECK: rnsbg %r2, %r3, 58, 61, 029; CHECK: br %r1430 %orb = or i32 %b, -6131 %and = and i32 %a, %orb32 ret i32 %and33}34 35; ...and again with i64.36define i64 @f4(i64 %a, i64 %b) {37; CHECK-LABEL: f4:38; CHECK: rnsbg %r2, %r3, 58, 61, 039; CHECK: br %r1440 %orb = or i64 %b, -6141 %and = and i64 %a, %orb42 ret i64 %and43}44 45; Test a case with just a left shift. This can't use RNSBG.46define i32 @f6(i32 %a, i32 %b) {47; CHECK-LABEL: f6:48; CHECK: sll {{%r[0-5]}}49; CHECK: nr {{%r[0-5]}}50; CHECK: br %r1451 %shrb = shl i32 %b, 2052 %and = and i32 %a, %shrb53 ret i32 %and54}55 56; ...and again with i64.57define i64 @f7(i64 %a, i64 %b) {58; CHECK-LABEL: f7:59; CHECK: sllg {{%r[0-5]}}60; CHECK: ngr {{%r[0-5]}}61; CHECK: br %r1462 %shrb = shl i64 %b, 2063 %and = and i64 %a, %shrb64 ret i64 %and65}66 67; Test a case with just a rotate. This can't use RNSBG.68define i32 @f8(i32 %a, i32 %b) {69; CHECK-LABEL: f8:70; CHECK: rll {{%r[0-5]}}71; CHECK: nr {{%r[0-5]}}72; CHECK: br %r1473 %shlb = shl i32 %b, 2274 %shrb = lshr i32 %b, 1075 %rotlb = or i32 %shlb, %shrb76 %and = and i32 %a, %rotlb77 ret i32 %and78}79 80; ...and again with i64, which can.81define i64 @f9(i64 %a, i64 %b) {82; CHECK-LABEL: f9:83; CHECK: rnsbg %r2, %r3, 0, 63, 4484; CHECK: br %r1485 %shlb = shl i64 %b, 4486 %shrb = lshr i64 %b, 2087 %rotlb = or i64 %shlb, %shrb88 %and = and i64 %a, %rotlb89 ret i64 %and90}91 92; Test a case with a left shift and OR, where the OR covers all shifted bits.93; We can do the whole thing using RNSBG.94define i32 @f10(i32 %a, i32 %b) {95; CHECK-LABEL: f10:96; CHECK: rnsbg %r2, %r3, 32, 56, 797; CHECK: br %r1498 %shlb = shl i32 %b, 799 %orb = or i32 %shlb, 127100 %and = and i32 %a, %orb101 ret i32 %and102}103 104; ...and again with i64.105define i64 @f11(i64 %a, i64 %b) {106; CHECK-LABEL: f11:107; CHECK: rnsbg %r2, %r3, 0, 56, 7108; CHECK: br %r14109 %shlb = shl i64 %b, 7110 %orb = or i64 %shlb, 127111 %and = and i64 %a, %orb112 ret i64 %and113}114 115; Test a case with a left shift and OR, where the OR doesn't cover all116; shifted bits. We can't use RNSBG for the shift, but we can for the OR117; and AND.118define i32 @f12(i32 %a, i32 %b) {119; CHECK-LABEL: f12:120; CHECK: sll %r3, 7121; CHECK: rnsbg %r2, %r3, 32, 57, 0122; CHECK: br %r14123 %shlb = shl i32 %b, 7124 %orb = or i32 %shlb, 63125 %and = and i32 %a, %orb126 ret i32 %and127}128 129; ...and again with i64.130define i64 @f13(i64 %a, i64 %b) {131; CHECK-LABEL: f13:132; CHECK: sllg [[REG:%r[01345]]], %r3, 7133; CHECK: rnsbg %r2, [[REG]], 0, 57, 0134; CHECK: br %r14135 %shlb = shl i64 %b, 7136 %orb = or i64 %shlb, 63137 %and = and i64 %a, %orb138 ret i64 %and139}140 141; Test a case with a right shift and OR, where the OR covers all the shifted142; bits. The whole thing can be done using RNSBG.143define i32 @f14(i32 %a, i32 %b) {144; CHECK-LABEL: f14:145; CHECK: rnsbg %r2, %r3, 60, 63, 37146; CHECK: br %r14147 %shrb = lshr i32 %b, 27148 %orb = or i32 %shrb, -16149 %and = and i32 %a, %orb150 ret i32 %and151}152 153; ...and again with i64.154define i64 @f15(i64 %a, i64 %b) {155; CHECK-LABEL: f15:156; CHECK: rnsbg %r2, %r3, 60, 63, 5157; CHECK: br %r14158 %shrb = lshr i64 %b, 59159 %orb = or i64 %shrb, -16160 %and = and i64 %a, %orb161 ret i64 %and162}163 164; Test a case with a right shift and OR, where the OR doesn't cover all the165; shifted bits. The shift needs to be done separately, but the OR and AND166; can use RNSBG.167define i32 @f16(i32 %a, i32 %b) {168; CHECK-LABEL: f16:169; CHECK: srl %r3, 29170; CHECK: rnsbg %r2, %r3, 60, 63, 0171; CHECK: br %r14172 %shrb = lshr i32 %b, 29173 %orb = or i32 %shrb, -16174 %and = and i32 %a, %orb175 ret i32 %and176}177 178; ...and again with i64.179define i64 @f17(i64 %a, i64 %b) {180; CHECK-LABEL: f17:181; CHECK: srlg [[REG:%r[01345]]], %r3, 61182; CHECK: rnsbg %r2, [[REG]], 60, 63, 0183; CHECK: br %r14184 %shrb = lshr i64 %b, 61185 %orb = or i64 %shrb, -16186 %and = and i64 %a, %orb187 ret i64 %and188}189 190; Test a combination involving an ASHR in which the sign bits matter.191; We can't use RNSBG for the ASHR in that case, but we can for the rest.192define i32 @f18(i32 %a, i32 %b, ptr %dest) {193; CHECK-LABEL: f18:194; CHECK: sra %r3, 4195; CHECK: rnsbg %r2, %r3, 32, 62, 1196; CHECK: br %r14197 %ashrb = ashr i32 %b, 4198 store i32 %ashrb, ptr %dest199 %shlb = shl i32 %ashrb, 1200 %orb = or i32 %shlb, 1201 %and = and i32 %a, %orb202 ret i32 %and203}204 205; ...and again with i64.206define i64 @f19(i64 %a, i64 %b, ptr %dest) {207; CHECK-LABEL: f19:208; CHECK: srag [[REG:%r[0145]]], %r3, 34209; CHECK: rnsbg %r2, [[REG]], 0, 62, 1210; CHECK: br %r14211 %ashrb = ashr i64 %b, 34212 store i64 %ashrb, ptr %dest213 %shlb = shl i64 %ashrb, 1214 %orb = or i64 %shlb, 1215 %and = and i64 %a, %orb216 ret i64 %and217}218 219; Test a combination involving an ASHR in which the sign bits don't matter.220define i32 @f20(i32 %a, i32 %b, ptr %dest) {221; CHECK-LABEL: f20:222; CHECK-NOT: lr223; CHECK: rnsbg %r2, %r3, 48, 62, 1224; CHECK: br %r14225 %ashrb = ashr i32 %b, 17226 store i32 %ashrb, ptr %dest227 %shlb = shl i32 %ashrb, 1228 %orb = or i32 %shlb, -65535229 %and = and i32 %a, %orb230 ret i32 %and231}232 233; ...and again with i64.234define i64 @f21(i64 %a, i64 %b, ptr %dest) {235; CHECK-LABEL: f21:236; CHECK: rnsbg %r2, %r0, 48, 62, 1237; CHECK: br %r14238 %ashrb = ashr i64 %b, 49239 store i64 %ashrb, ptr %dest240 %shlb = shl i64 %ashrb, 1241 %orb = or i64 %shlb, -65535242 %and = and i64 %a, %orb243 ret i64 %and244}245 246; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.247define i64 @f22(i64 %a, i64 %b) {248; CHECK-LABEL: f22:249; CHECK: rnsbg %r2, %r3, 60, 54, 9250; CHECK: br %r14251 %shlb = shl i64 %b, 5252 %orb = or i64 %shlb, 31253 %shlorb = shl i64 %orb, 4254 %shrorb = lshr i64 %orb, 60255 %rotlorb = or i64 %shlorb, %shrorb256 %and = and i64 %a, %rotlorb257 ret i64 %and258}259 260; Check the handling of zext and AND, which isn't suitable for RNSBG.261define i64 @f23(i64 %a, i32 %b) {262; CHECK-LABEL: f23:263; CHECK-NOT: rnsbg264; CHECK: br %r14265 %add = add i32 %b, 1266 %ext = zext i32 %add to i64267 %and = and i64 %a, %ext268 ret i64 %and269}270