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1; Test an i64 0/-1 SELECTCCC for every floating-point condition.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s4 5; Test CC in { 0 }6define i64 @f1(float %a, float %b) {7; CHECK-LABEL: f1:8; CHECK: ipm [[REG:%r[0-5]]]9; CHECK-NEXT: afi [[REG]], -26843545610; CHECK-NEXT: sllg [[REG]], [[REG]], 3211; CHECK-NEXT: srag %r2, [[REG]], 6312; CHECK: br %r1413 %cond = fcmp oeq float %a, %b14 %res = select i1 %cond, i64 -1, i64 015 ret i64 %res16}17 18; Test CC in { 1 }19define i64 @f2(float %a, float %b) {20; CHECK-LABEL: f2:21; CHECK: ipm [[REG:%r[0-5]]]22; CHECK-NEXT: xilf [[REG]], 26843545623; CHECK-NEXT: afi [[REG]], -26843545624; CHECK-NEXT: sllg [[REG]], [[REG]], 3225; CHECK-NEXT: srag %r2, [[REG]], 6326; CHECK: br %r1427 %cond = fcmp olt float %a, %b28 %res = select i1 %cond, i64 -1, i64 029 ret i64 %res30}31 32; Test CC in { 0, 1 }33define i64 @f3(float %a, float %b) {34; CHECK-LABEL: f3:35; CHECK: ipm [[REG:%r[0-5]]]36; CHECK-NEXT: afi [[REG]], -53687091237; CHECK-NEXT: sllg [[REG]], [[REG]], 3238; CHECK-NEXT: srag %r2, [[REG]], 6339; CHECK: br %r1440 %cond = fcmp ole float %a, %b41 %res = select i1 %cond, i64 -1, i64 042 ret i64 %res43}44 45; Test CC in { 2 }46define i64 @f4(float %a, float %b) {47; CHECK-LABEL: f4:48; CHECK: ipm [[REG:%r[0-5]]]49; CHECK-NEXT: xilf [[REG]], 26843545650; CHECK-NEXT: afi [[REG]], 134217728051; CHECK-NEXT: sllg [[REG]], [[REG]], 3252; CHECK-NEXT: srag %r2, [[REG]], 6353; CHECK: br %r1454 %cond = fcmp ogt float %a, %b55 %res = select i1 %cond, i64 -1, i64 056 ret i64 %res57}58 59; Test CC in { 0, 2 }60define i64 @f5(float %a, float %b) {61; CHECK-LABEL: f5:62; CHECK: ipm [[REG:%r[0-5]]]63; CHECK-NEXT: xilf [[REG]], 429496729564; CHECK-NEXT: sllg [[REG]], [[REG]], 3565; CHECK-NEXT: srag %r2, [[REG]], 6366; CHECK: br %r1467 %cond = fcmp oge float %a, %b68 %res = select i1 %cond, i64 -1, i64 069 ret i64 %res70}71 72; Test CC in { 1, 2 }73define i64 @f6(float %a, float %b) {74; CHECK-LABEL: f6:75; CHECK: ipm [[REG:%r[0-5]]]76; CHECK-NEXT: afi [[REG]], 26843545677; CHECK-NEXT: sllg [[REG]], [[REG]], 3478; CHECK-NEXT: srag %r2, [[REG]], 6379; CHECK: br %r1480 %cond = fcmp one float %a, %b81 %res = select i1 %cond, i64 -1, i64 082 ret i64 %res83}84 85; Test CC in { 0, 1, 2 }86define i64 @f7(float %a, float %b) {87; CHECK-LABEL: f7:88; CHECK: ipm [[REG:%r[0-5]]]89; CHECK-NEXT: afi [[REG]], -80530636890; CHECK-NEXT: sllg [[REG]], [[REG]], 3291; CHECK-NEXT: srag %r2, [[REG]], 6392; CHECK: br %r1493 %cond = fcmp ord float %a, %b94 %res = select i1 %cond, i64 -1, i64 095 ret i64 %res96}97 98; Test CC in { 3 }99define i64 @f8(float %a, float %b) {100; CHECK-LABEL: f8:101; CHECK: ipm [[REG:%r[0-5]]]102; CHECK-NEXT: afi [[REG]], 1342177280103; CHECK-NEXT: sllg [[REG]], [[REG]], 32104; CHECK-NEXT: srag %r2, [[REG]], 63105; CHECK: br %r14106 %cond = fcmp uno float %a, %b107 %res = select i1 %cond, i64 -1, i64 0108 ret i64 %res109}110 111; Test CC in { 0, 3 }112define i64 @f9(float %a, float %b) {113; CHECK-LABEL: f9:114; CHECK: ipm [[REG:%r[0-5]]]115; CHECK-NEXT: afi [[REG]], -268435456116; CHECK-NEXT: sllg [[REG]], [[REG]], 34117; CHECK-NEXT: srag %r2, [[REG]], 63118; CHECK: br %r14119 %cond = fcmp ueq float %a, %b120 %res = select i1 %cond, i64 -1, i64 0121 ret i64 %res122}123 124; Test CC in { 1, 3 }125define i64 @f10(float %a, float %b) {126; CHECK-LABEL: f10:127; CHECK: ipm [[REG:%r[0-5]]]128; CHECK-NEXT: sllg [[REG]], [[REG]], 35129; CHECK-NEXT: srag %r2, [[REG]], 63130; CHECK: br %r14131 %cond = fcmp ult float %a, %b132 %res = select i1 %cond, i64 -1, i64 0133 ret i64 %res134}135 136; Test CC in { 0, 1, 3 }137define i64 @f11(float %a, float %b) {138; CHECK-LABEL: f11:139; CHECK: ipm [[REG:%r[0-5]]]140; CHECK-NEXT: xilf [[REG]], 268435456141; CHECK-NEXT: afi [[REG]], -805306368142; CHECK-NEXT: sllg [[REG]], [[REG]], 32143; CHECK-NEXT: srag %r2, [[REG]], 63144; CHECK: br %r14145 %cond = fcmp ule float %a, %b146 %res = select i1 %cond, i64 -1, i64 0147 ret i64 %res148}149 150; Test CC in { 2, 3 }151define i64 @f12(float %a, float %b) {152; CHECK-LABEL: f12:153; CHECK: ipm [[REG:%r[0-5]]]154; CHECK-NEXT: sllg [[REG]], [[REG]], 34155; CHECK-NEXT: srag %r2, [[REG]], 63156; CHECK: br %r14157 %cond = fcmp ugt float %a, %b158 %res = select i1 %cond, i64 -1, i64 0159 ret i64 %res160}161 162; Test CC in { 0, 2, 3 }163define i64 @f13(float %a, float %b) {164; CHECK-LABEL: f13:165; CHECK: ipm [[REG:%r[0-5]]]166; CHECK-NEXT: xilf [[REG]], 268435456167; CHECK-NEXT: afi [[REG]], 1879048192168; CHECK-NEXT: sllg [[REG]], [[REG]], 32169; CHECK-NEXT: srag %r2, [[REG]], 63170; CHECK: br %r14171 %cond = fcmp uge float %a, %b172 %res = select i1 %cond, i64 -1, i64 0173 ret i64 %res174}175 176; Test CC in { 1, 2, 3 }177define i64 @f14(float %a, float %b) {178; CHECK-LABEL: f14:179; CHECK: ipm [[REG:%r[0-5]]]180; CHECK-NEXT: afi [[REG]], 1879048192181; CHECK-NEXT: sllg [[REG]], [[REG]], 32182; CHECK-NEXT: srag %r2, [[REG]], 63183; CHECK: br %r14184 %cond = fcmp une float %a, %b185 %res = select i1 %cond, i64 -1, i64 0186 ret i64 %res187}188