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1; Test SETCC for every floating-point condition. The tests here assume that2; RISBLG isn't available.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s5 6; Test CC in { 0 }7define i32 @f1(float %a, float %b) {8; CHECK-LABEL: f1:9; CHECK: ipm %r210; CHECK-NEXT: afi %r2, -26843545611; CHECK-NEXT: srl %r2, 3112; CHECK: br %r1413 %cond = fcmp oeq float %a, %b14 %res = zext i1 %cond to i3215 ret i32 %res16}17 18; Test CC in { 1 }19define i32 @f2(float %a, float %b) {20; CHECK-LABEL: f2:21; CHECK: ipm %r222; CHECK-NEXT: xilf %r2, 26843545623; CHECK-NEXT: afi %r2, -26843545624; CHECK-NEXT: srl %r2, 3125; CHECK: br %r1426 %cond = fcmp olt float %a, %b27 %res = zext i1 %cond to i3228 ret i32 %res29}30 31; Test CC in { 0, 1 }32define i32 @f3(float %a, float %b) {33; CHECK-LABEL: f3:34; CHECK: ipm %r235; CHECK-NEXT: afi %r2, -53687091236; CHECK-NEXT: srl %r2, 3137; CHECK: br %r1438 %cond = fcmp ole float %a, %b39 %res = zext i1 %cond to i3240 ret i32 %res41}42 43; Test CC in { 2 }44define i32 @f4(float %a, float %b) {45; CHECK-LABEL: f4:46; CHECK: ipm %r247; CHECK-NEXT: xilf %r2, 26843545648; CHECK-NEXT: afi %r2, 134217728049; CHECK-NEXT: srl %r2, 3150; CHECK: br %r1451 %cond = fcmp ogt float %a, %b52 %res = zext i1 %cond to i3253 ret i32 %res54}55 56; Test CC in { 0, 2 }57define i32 @f5(float %a, float %b) {58; CHECK-LABEL: f5:59; CHECK: ipm [[REG:%r[0-5]]]60; CHECK-NEXT: xilf [[REG]], 429496729561; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3662; CHECK: br %r1463 %cond = fcmp oge float %a, %b64 %res = zext i1 %cond to i3265 ret i32 %res66}67 68; Test CC in { 1, 2 }69define i32 @f6(float %a, float %b) {70; CHECK-LABEL: f6:71; CHECK: ipm [[REG:%r[0-5]]]72; CHECK-NEXT: afi [[REG]], 26843545673; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3574; CHECK: br %r1475 %cond = fcmp one float %a, %b76 %res = zext i1 %cond to i3277 ret i32 %res78}79 80; Test CC in { 0, 1, 2 }81define i32 @f7(float %a, float %b) {82; CHECK-LABEL: f7:83; CHECK: ipm %r284; CHECK-NEXT: afi %r2, -80530636885; CHECK-NEXT: srl %r2, 3186; CHECK: br %r1487 %cond = fcmp ord float %a, %b88 %res = zext i1 %cond to i3289 ret i32 %res90}91 92; Test CC in { 3 }93define i32 @f8(float %a, float %b) {94; CHECK-LABEL: f8:95; CHECK: ipm %r296; CHECK-NEXT: afi %r2, 134217728097; CHECK-NEXT: srl %r2, 3198; CHECK: br %r1499 %cond = fcmp uno float %a, %b100 %res = zext i1 %cond to i32101 ret i32 %res102}103 104; Test CC in { 0, 3 }105define i32 @f9(float %a, float %b) {106; CHECK-LABEL: f9:107; CHECK: ipm [[REG:%r[0-5]]]108; CHECK-NEXT: afi [[REG]], -268435456109; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35110; CHECK: br %r14111 %cond = fcmp ueq float %a, %b112 %res = zext i1 %cond to i32113 ret i32 %res114}115 116; Test CC in { 1, 3 }117define i32 @f10(float %a, float %b) {118; CHECK-LABEL: f10:119; CHECK: ipm [[REG:%r[0-5]]]120; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36121; CHECK: br %r14122 %cond = fcmp ult float %a, %b123 %res = zext i1 %cond to i32124 ret i32 %res125}126 127; Test CC in { 0, 1, 3 }128define i32 @f11(float %a, float %b) {129; CHECK-LABEL: f11:130; CHECK: ipm %r2131; CHECK-NEXT: xilf %r2, 268435456132; CHECK-NEXT: afi %r2, -805306368133; CHECK-NEXT: srl %r2, 31134; CHECK: br %r14135 %cond = fcmp ule float %a, %b136 %res = zext i1 %cond to i32137 ret i32 %res138}139 140; Test CC in { 2, 3 }141define i32 @f12(float %a, float %b) {142; CHECK-LABEL: f12:143; CHECK: ipm [[REG:%r[0-5]]]144; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35145; CHECK: br %r14146 %cond = fcmp ugt float %a, %b147 %res = zext i1 %cond to i32148 ret i32 %res149}150 151; Test CC in { 0, 2, 3 }152define i32 @f13(float %a, float %b) {153; CHECK-LABEL: f13:154; CHECK: ipm %r2155; CHECK-NEXT: xilf %r2, 268435456156; CHECK-NEXT: afi %r2, 1879048192157; CHECK-NEXT: srl %r2, 31158; CHECK: br %r14159 %cond = fcmp uge float %a, %b160 %res = zext i1 %cond to i32161 ret i32 %res162}163 164; Test CC in { 1, 2, 3 }165define i32 @f14(float %a, float %b) {166; CHECK-LABEL: f14:167; CHECK: ipm %r2168; CHECK-NEXT: afi %r2, 1879048192169; CHECK-NEXT: srl %r2, 31170; CHECK: br %r14171 %cond = fcmp une float %a, %b172 %res = zext i1 %cond to i32173 ret i32 %res174}175