174 lines · plain
1; Test SETCC with an i64 result for every floating-point condition.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s4 5; Test CC in { 0 }6define i64 @f1(float %a, float %b) {7; CHECK-LABEL: f1:8; CHECK: ipm [[REG:%r[0-5]]]9; CHECK-NEXT: afi [[REG]], -26843545610; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3311; CHECK: br %r1412 %cond = fcmp oeq float %a, %b13 %res = zext i1 %cond to i6414 ret i64 %res15}16 17; Test CC in { 1 }18define i64 @f2(float %a, float %b) {19; CHECK-LABEL: f2:20; CHECK: ipm [[REG:%r[0-5]]]21; CHECK-NEXT: xilf [[REG]], 26843545622; CHECK-NEXT: afi [[REG]], -26843545623; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3324; CHECK: br %r1425 %cond = fcmp olt float %a, %b26 %res = zext i1 %cond to i6427 ret i64 %res28}29 30; Test CC in { 0, 1 }31define i64 @f3(float %a, float %b) {32; CHECK-LABEL: f3:33; CHECK: ipm [[REG:%r[0-5]]]34; CHECK-NEXT: afi [[REG]], -53687091235; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3336; CHECK: br %r1437 %cond = fcmp ole float %a, %b38 %res = zext i1 %cond to i6439 ret i64 %res40}41 42; Test CC in { 2 }43define i64 @f4(float %a, float %b) {44; CHECK-LABEL: f4:45; CHECK: ipm [[REG:%r[0-5]]]46; CHECK-NEXT: xilf [[REG]], 26843545647; CHECK-NEXT: afi [[REG]], 134217728048; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3349; CHECK: br %r1450 %cond = fcmp ogt float %a, %b51 %res = zext i1 %cond to i6452 ret i64 %res53}54 55; Test CC in { 0, 2 }56define i64 @f5(float %a, float %b) {57; CHECK-LABEL: f5:58; CHECK: ipm [[REG:%r[0-5]]]59; CHECK-NEXT: xilf [[REG]], 429496729560; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3661; CHECK: br %r1462 %cond = fcmp oge float %a, %b63 %res = zext i1 %cond to i6464 ret i64 %res65}66 67; Test CC in { 1, 2 }68define i64 @f6(float %a, float %b) {69; CHECK-LABEL: f6:70; CHECK: ipm [[REG:%r[0-5]]]71; CHECK-NEXT: afi [[REG]], 26843545672; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3573; CHECK: br %r1474 %cond = fcmp one float %a, %b75 %res = zext i1 %cond to i6476 ret i64 %res77}78 79; Test CC in { 0, 1, 2 }80define i64 @f7(float %a, float %b) {81; CHECK-LABEL: f7:82; CHECK: ipm [[REG:%r[0-5]]]83; CHECK-NEXT: afi [[REG]], -80530636884; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3385; CHECK: br %r1486 %cond = fcmp ord float %a, %b87 %res = zext i1 %cond to i6488 ret i64 %res89}90 91; Test CC in { 3 }92define i64 @f8(float %a, float %b) {93; CHECK-LABEL: f8:94; CHECK: ipm [[REG:%r[0-5]]]95; CHECK-NEXT: afi [[REG]], 134217728096; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 3397; CHECK: br %r1498 %cond = fcmp uno float %a, %b99 %res = zext i1 %cond to i64100 ret i64 %res101}102 103; Test CC in { 0, 3 }104define i64 @f9(float %a, float %b) {105; CHECK-LABEL: f9:106; CHECK: ipm [[REG:%r[0-5]]]107; CHECK-NEXT: afi [[REG]], -268435456108; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35109; CHECK: br %r14110 %cond = fcmp ueq float %a, %b111 %res = zext i1 %cond to i64112 ret i64 %res113}114 115; Test CC in { 1, 3 }116define i64 @f10(float %a, float %b) {117; CHECK-LABEL: f10:118; CHECK: ipm [[REG:%r[0-5]]]119; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36120; CHECK: br %r14121 %cond = fcmp ult float %a, %b122 %res = zext i1 %cond to i64123 ret i64 %res124}125 126; Test CC in { 0, 1, 3 }127define i64 @f11(float %a, float %b) {128; CHECK-LABEL: f11:129; CHECK: ipm [[REG:%r[0-5]]]130; CHECK-NEXT: xilf [[REG]], 268435456131; CHECK-NEXT: afi [[REG]], -805306368132; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33133; CHECK: br %r14134 %cond = fcmp ule float %a, %b135 %res = zext i1 %cond to i64136 ret i64 %res137}138 139; Test CC in { 2, 3 }140define i64 @f12(float %a, float %b) {141; CHECK-LABEL: f12:142; CHECK: ipm [[REG:%r[0-5]]]143; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35144; CHECK: br %r14145 %cond = fcmp ugt float %a, %b146 %res = zext i1 %cond to i64147 ret i64 %res148}149 150; Test CC in { 0, 2, 3 }151define i64 @f13(float %a, float %b) {152; CHECK-LABEL: f13:153; CHECK: ipm [[REG:%r[0-5]]]154; CHECK-NEXT: xilf [[REG]], 268435456155; CHECK-NEXT: afi [[REG]], 1879048192156; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33157; CHECK: br %r14158 %cond = fcmp uge float %a, %b159 %res = zext i1 %cond to i64160 ret i64 %res161}162 163; Test CC in { 1, 2, 3 }164define i64 @f14(float %a, float %b) {165; CHECK-LABEL: f14:166; CHECK: ipm [[REG:%r[0-5]]]167; CHECK-NEXT: afi [[REG]], 1879048192168; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33169; CHECK: br %r14170 %cond = fcmp une float %a, %b171 %res = zext i1 %cond to i64172 ret i64 %res173}174