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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Test compound shifts.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s5 6; Test a shift right followed by a sign extension. This can use two shifts.7define i64 @f1(i32 %a) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d11; CHECK-NEXT: risbg %r0, %r2, 63, 191, 6312; CHECK-NEXT: lcgr %r2, %r013; CHECK-NEXT: br %r1414 %shr = lshr i32 %a, 115 %trunc = trunc i32 %shr to i116 %ext = sext i1 %trunc to i6417 ret i64 %ext18}19 20; ...and again with the highest shift count that doesn't reduce to an21; ashr/sext pair.22define i64 @f2(i32 %a) {23; CHECK-LABEL: f2:24; CHECK: # %bb.0:25; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d26; CHECK-NEXT: risbg %r0, %r2, 63, 191, 3427; CHECK-NEXT: lcgr %r2, %r028; CHECK-NEXT: br %r1429 %shr = lshr i32 %a, 3030 %trunc = trunc i32 %shr to i131 %ext = sext i1 %trunc to i6432 ret i64 %ext33}34 35; Test a left shift that of an extended right shift in a case where folding36; is possible.37define i64 @f3(i32 %a) {38; CHECK-LABEL: f3:39; CHECK: # %bb.0:40; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d41; CHECK-NEXT: risbg %r2, %r2, 27, 181, 942; CHECK-NEXT: br %r1443 %shr = lshr i32 %a, 144 %ext = zext i32 %shr to i6445 %shl = shl i64 %ext, 1046 %and = and i64 %shl, 13743895296047 ret i64 %and48}49 50; ...and again with a larger right shift.51define i64 @f4(i32 %a) {52; CHECK-LABEL: f4:53; CHECK: # %bb.0:54; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d55; CHECK-NEXT: risbg %r2, %r2, 30, 158, 356; CHECK-NEXT: br %r1457 %shr = lshr i32 %a, 3058 %ext = sext i32 %shr to i6459 %shl = shl i64 %ext, 3360 %and = and i64 %shl, 858993459261 ret i64 %and62}63 64; Repeat the previous test in a case where all bits outside the65; bottom 3 matter.66define i64 @f5(i32 %a) {67; CHECK-LABEL: f5:68; CHECK: # %bb.0:69; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d70; CHECK-NEXT: risbg %r2, %r2, 29, 158, 371; CHECK-NEXT: lhi %r2, 772; CHECK-NEXT: br %r1473 %shr = lshr i32 %a, 3074 %ext = sext i32 %shr to i6475 %shl = shl i64 %ext, 3376 %or = or i64 %shl, 777 ret i64 %or78}79 80; Test that SRA gets replaced with SRL if the sign bit is the only one81; that matters.82define i64 @f6(i64 %a) {83; CHECK-LABEL: f6:84; CHECK: # %bb.0:85; CHECK-NEXT: risbg %r2, %r2, 55, 183, 1986; CHECK-NEXT: br %r1487 %shl = shl i64 %a, 1088 %shr = ashr i64 %shl, 6089 %and = and i64 %shr, 25690 ret i64 %and91}92 93; Test another form of f1.94define i64 @f7(i32 %a) {95; CHECK-LABEL: f7:96; CHECK: # %bb.0:97; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d98; CHECK-NEXT: sllg %r0, %r2, 6299; CHECK-NEXT: srag %r2, %r0, 63100; CHECK-NEXT: br %r14101 %1 = shl i32 %a, 30102 %sext = ashr i32 %1, 31103 %ext = sext i32 %sext to i64104 ret i64 %ext105}106