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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Test removal of AND operations that don't affect last 6 bits of shift amount3; operand.4;5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s6 7; Test that AND is not removed when some lower 6 bits are not set.8define i32 @f1(i32 %a, i32 %sh) {9; CHECK-LABEL: f1:10; CHECK: # %bb.0:11; CHECK-NEXT: nill %r3, 3112; CHECK-NEXT: sll %r2, 0(%r3)13; CHECK-NEXT: br %r1414 %and = and i32 %sh, 3115 %shift = shl i32 %a, %and16 ret i32 %shift17}18 19; Test removal of AND mask with only bottom 6 bits set.20define i32 @f2(i32 %a, i32 %sh) {21; CHECK-LABEL: f2:22; CHECK: # %bb.0:23; CHECK-NEXT: sll %r2, 0(%r3)24; CHECK-NEXT: br %r1425 %and = and i32 %sh, 6326 %shift = shl i32 %a, %and27 ret i32 %shift28}29 30; Test removal of AND mask including but not limited to bottom 6 bits.31define i32 @f3(i32 %a, i32 %sh) {32; CHECK-LABEL: f3:33; CHECK: # %bb.0:34; CHECK-NEXT: sll %r2, 0(%r3)35; CHECK-NEXT: br %r1436 %and = and i32 %sh, 25537 %shift = shl i32 %a, %and38 ret i32 %shift39}40 41; Test removal of AND mask from SRA.42define i32 @f4(i32 %a, i32 %sh) {43; CHECK-LABEL: f4:44; CHECK: # %bb.0:45; CHECK-NEXT: sra %r2, 0(%r3)46; CHECK-NEXT: br %r1447 %and = and i32 %sh, 6348 %shift = ashr i32 %a, %and49 ret i32 %shift50}51 52; Test removal of AND mask from SRL.53define i32 @f5(i32 %a, i32 %sh) {54; CHECK-LABEL: f5:55; CHECK: # %bb.0:56; CHECK-NEXT: srl %r2, 0(%r3)57; CHECK-NEXT: br %r1458 %and = and i32 %sh, 6359 %shift = lshr i32 %a, %and60 ret i32 %shift61}62 63; Test removal of AND mask from SLLG.64define i64 @f6(i64 %a, i64 %sh) {65; CHECK-LABEL: f6:66; CHECK: # %bb.0:67; CHECK-NEXT: sllg %r2, %r2, 0(%r3)68; CHECK-NEXT: br %r1469 %and = and i64 %sh, 6370 %shift = shl i64 %a, %and71 ret i64 %shift72}73 74; Test removal of AND mask from SRAG.75define i64 @f7(i64 %a, i64 %sh) {76; CHECK-LABEL: f7:77; CHECK: # %bb.0:78; CHECK-NEXT: srag %r2, %r2, 0(%r3)79; CHECK-NEXT: br %r1480 %and = and i64 %sh, 6381 %shift = ashr i64 %a, %and82 ret i64 %shift83}84 85; Test removal of AND mask from SRLG.86define i64 @f8(i64 %a, i64 %sh) {87; CHECK-LABEL: f8:88; CHECK: # %bb.0:89; CHECK-NEXT: srlg %r2, %r2, 0(%r3)90; CHECK-NEXT: br %r1491 %and = and i64 %sh, 6392 %shift = lshr i64 %a, %and93 ret i64 %shift94}95 96; Test that AND with two register operands is not affected.97define i32 @f9(i32 %a, i32 %b, i32 %sh) {98; CHECK-LABEL: f9:99; CHECK: # %bb.0:100; CHECK-NEXT: nr %r3, %r4101; CHECK-NEXT: sll %r2, 0(%r3)102; CHECK-NEXT: br %r14103 %and = and i32 %sh, %b104 %shift = shl i32 %a, %and105 ret i32 %shift106}107 108; Test that AND is not entirely removed if the result is reused.109define i32 @f10(i32 %a, i32 %sh) {110; CHECK-LABEL: f10:111; CHECK: # %bb.0:112; CHECK-NEXT: sll %r2, 0(%r3)113; CHECK-NEXT: nilf %r3, 63114; CHECK-NEXT: ar %r2, %r3115; CHECK-NEXT: br %r14116 %and = and i32 %sh, 63117 %shift = shl i32 %a, %and118 %reuse = add i32 %and, %shift119 ret i32 %reuse120}121 122define i128 @f11(i128 %a, i32 %sh) {123; CHECK-LABEL: f11:124; CHECK: # %bb.0:125; CHECK-NEXT: vlvgp %v1, %r4, %r4126; CHECK-NEXT: vl %v0, 0(%r3), 3127; CHECK-NEXT: vrepb %v1, %v1, 15128; CHECK-NEXT: vslb %v0, %v0, %v1129; CHECK-NEXT: vsl %v0, %v0, %v1130; CHECK-NEXT: vst %v0, 0(%r2), 3131; CHECK-NEXT: br %r14132 %and = and i32 %sh, 127133 %ext = zext i32 %and to i128134 %shift = shl i128 %a, %ext135 ret i128 %shift136}137 138define i128 @f12(i128 %a, i32 %sh) {139; CHECK-LABEL: f12:140; CHECK: # %bb.0:141; CHECK-NEXT: vlvgp %v1, %r4, %r4142; CHECK-NEXT: vl %v0, 0(%r3), 3143; CHECK-NEXT: vrepb %v1, %v1, 15144; CHECK-NEXT: vsrlb %v0, %v0, %v1145; CHECK-NEXT: vsrl %v0, %v0, %v1146; CHECK-NEXT: vst %v0, 0(%r2), 3147; CHECK-NEXT: br %r14148 %and = and i32 %sh, 127149 %ext = zext i32 %and to i128150 %shift = lshr i128 %a, %ext151 ret i128 %shift152}153 154define i128 @f13(i128 %a, i32 %sh) {155; CHECK-LABEL: f13:156; CHECK: # %bb.0:157; CHECK-NEXT: vlvgp %v1, %r4, %r4158; CHECK-NEXT: vl %v0, 0(%r3), 3159; CHECK-NEXT: vrepb %v1, %v1, 15160; CHECK-NEXT: vsrab %v0, %v0, %v1161; CHECK-NEXT: vsra %v0, %v0, %v1162; CHECK-NEXT: vst %v0, 0(%r2), 3163; CHECK-NEXT: br %r14164 %and = and i32 %sh, 127165 %ext = zext i32 %and to i128166 %shift = ashr i128 %a, %ext167 ret i128 %shift168}169 170