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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test 128-bit shift right logica in vector registers on z133;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; Shift right logical immediate (general case).7define i128 @f1(i128 %a) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r3), 311; CHECK-NEXT: vrepib %v1, 10012; CHECK-NEXT: vsrlb %v0, %v0, %v113; CHECK-NEXT: vsrl %v0, %v0, %v114; CHECK-NEXT: vst %v0, 0(%r2), 315; CHECK-NEXT: br %r1416 %res = lshr i128 %a, 10017 ret i128 %res18}19 20; Shift right logical immediate (< 8 bits).21define i128 @f2(i128 %a) {22; CHECK-LABEL: f2:23; CHECK: # %bb.0:24; CHECK-NEXT: vl %v0, 0(%r3), 325; CHECK-NEXT: vrepib %v1, 726; CHECK-NEXT: vsrl %v0, %v0, %v127; CHECK-NEXT: vst %v0, 0(%r2), 328; CHECK-NEXT: br %r1429 %res = lshr i128 %a, 730 ret i128 %res31}32 33; Shift right logical immediate (full bytes).34define i128 @f3(i128 %a) {35; CHECK-LABEL: f3:36; CHECK: # %bb.0:37; CHECK-NEXT: vl %v0, 0(%r3), 338; CHECK-NEXT: vrepib %v1, 3239; CHECK-NEXT: vsrlb %v0, %v0, %v140; CHECK-NEXT: vst %v0, 0(%r2), 341; CHECK-NEXT: br %r1442 %res = lshr i128 %a, 3243 ret i128 %res44}45 46; Shift right logical variable.47define i128 @f4(i128 %a, i128 %sh) {48; CHECK-LABEL: f4:49; CHECK: # %bb.0:50; CHECK-NEXT: l %r0, 12(%r4)51; CHECK-NEXT: vlvgp %v1, %r0, %r052; CHECK-NEXT: vl %v0, 0(%r3), 353; CHECK-NEXT: vrepb %v1, %v1, 1554; CHECK-NEXT: vsrlb %v0, %v0, %v155; CHECK-NEXT: vsrl %v0, %v0, %v156; CHECK-NEXT: vst %v0, 0(%r2), 357; CHECK-NEXT: br %r1458 %res = lshr i128 %a, %sh59 ret i128 %res60}61 62; Test removal of AND mask with only bottom 7 bits set.63define i128 @f5(i128 %a, i128 %sh) {64; CHECK-LABEL: f5:65; CHECK: # %bb.0:66; CHECK-NEXT: l %r0, 12(%r4)67; CHECK-NEXT: vlvgp %v1, %r0, %r068; CHECK-NEXT: vl %v0, 0(%r3), 369; CHECK-NEXT: vrepb %v1, %v1, 1570; CHECK-NEXT: vsrlb %v0, %v0, %v171; CHECK-NEXT: vsrl %v0, %v0, %v172; CHECK-NEXT: vst %v0, 0(%r2), 373; CHECK-NEXT: br %r1474 %and = and i128 %sh, 12775 %shift = lshr i128 %a, %and76 ret i128 %shift77}78 79; Test removal of AND mask including but not limited to bottom 7 bits.80define i128 @f6(i128 %a, i128 %sh) {81; CHECK-LABEL: f6:82; CHECK: # %bb.0:83; CHECK-NEXT: l %r0, 12(%r4)84; CHECK-NEXT: vlvgp %v1, %r0, %r085; CHECK-NEXT: vl %v0, 0(%r3), 386; CHECK-NEXT: vrepb %v1, %v1, 1587; CHECK-NEXT: vsrlb %v0, %v0, %v188; CHECK-NEXT: vsrl %v0, %v0, %v189; CHECK-NEXT: vst %v0, 0(%r2), 390; CHECK-NEXT: br %r1491 %and = and i128 %sh, 51192 %shift = lshr i128 %a, %and93 ret i128 %shift94}95 96; Test that AND is not removed when some lower 7 bits are not set.97define i128 @f7(i128 %a, i128 %sh) {98; CHECK-LABEL: f7:99; CHECK: # %bb.0:100; CHECK-NEXT: lhi %r0, 63101; CHECK-NEXT: n %r0, 12(%r4)102; CHECK-NEXT: vlvgp %v1, %r0, %r0103; CHECK-NEXT: vl %v0, 0(%r3), 3104; CHECK-NEXT: vrepb %v1, %v1, 15105; CHECK-NEXT: vsrlb %v0, %v0, %v1106; CHECK-NEXT: vsrl %v0, %v0, %v1107; CHECK-NEXT: vst %v0, 0(%r2), 3108; CHECK-NEXT: br %r14109 %and = and i128 %sh, 63110 %shift = lshr i128 %a, %and111 ret i128 %shift112}113 114; Test that AND with two register operands is not affected.115define i128 @f8(i128 %a, i128 %b, i128 %sh) {116; CHECK-LABEL: f8:117; CHECK: # %bb.0:118; CHECK-NEXT: vl %v1, 0(%r4), 3119; CHECK-NEXT: vl %v2, 0(%r5), 3120; CHECK-NEXT: vn %v1, %v2, %v1121; CHECK-NEXT: vlgvf %r0, %v1, 3122; CHECK-NEXT: vlvgp %v1, %r0, %r0123; CHECK-NEXT: vl %v0, 0(%r3), 3124; CHECK-NEXT: vrepb %v1, %v1, 15125; CHECK-NEXT: vsrlb %v0, %v0, %v1126; CHECK-NEXT: vsrl %v0, %v0, %v1127; CHECK-NEXT: vst %v0, 0(%r2), 3128; CHECK-NEXT: br %r14129 %and = and i128 %sh, %b130 %shift = lshr i128 %a, %and131 ret i128 %shift132}133 134; Test that AND is not entirely removed if the result is reused.135define i128 @f9(i128 %a, i128 %sh) {136; CHECK-LABEL: f9:137; CHECK: # %bb.0:138; CHECK-NEXT: larl %r1, .LCPI8_0139; CHECK-NEXT: vl %v1, 0(%r4), 3140; CHECK-NEXT: vl %v2, 0(%r1), 3141; CHECK-NEXT: vn %v1, %v1, %v2142; CHECK-NEXT: vlgvf %r0, %v1, 3143; CHECK-NEXT: vlvgp %v2, %r0, %r0144; CHECK-NEXT: vl %v0, 0(%r3), 3145; CHECK-NEXT: vrepb %v2, %v2, 15146; CHECK-NEXT: vsrlb %v0, %v0, %v2147; CHECK-NEXT: vsrl %v0, %v0, %v2148; CHECK-NEXT: vaq %v0, %v1, %v0149; CHECK-NEXT: vst %v0, 0(%r2), 3150; CHECK-NEXT: br %r14151 %and = and i128 %sh, 127152 %shift = lshr i128 %a, %and153 %reuse = add i128 %and, %shift154 ret i128 %reuse155}156 157