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1; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s2; RUN: llc < %s -mtriple=s390x-linux-gnu -O0 -verify-machineinstrs | FileCheck --check-prefix=CHECK-O0 %s3 4@var = global i32 05 6; Test how llvm handles return type of {i16, i8}. The return value will be7; passed in %r2 and %r3.8; CHECK-LABEL: test:9; CHECK: st %r210; CHECK: brasl %r14, gen11; CHECK-DAG: lhr %{{r[0,2]+}}, %r212; CHECK-DAG: lbr %{{r[0,2]+}}, %r313; CHECK: ar %r2, %r014; CHECK-O0-LABEL: test15; CHECK-O0: st %r216; CHECK-O0: brasl %r14, gen17; CHECK-O0-DAG: lhr %r2, %r218; CHECK-O0-DAG: lbr %[[REG2:r[0-9]+]], %r319; CHECK-O0: ar %r2, %[[REG2]]20define i16 @test(i32 %key) {21entry:22 %key.addr = alloca i32, align 423 store i32 %key, ptr %key.addr, align 424 %0 = load i32, ptr %key.addr, align 425 %call = call swiftcc { i16, i8 } @gen(i32 %0)26 %v3 = extractvalue { i16, i8 } %call, 027 %v1 = sext i16 %v3 to i3228 %v5 = extractvalue { i16, i8 } %call, 129 %v2 = sext i8 %v5 to i3230 %add = add nsw i32 %v1, %v231 %conv = trunc i32 %add to i1632 ret i16 %conv33}34 35declare swiftcc { i16, i8 } @gen(i32)36 37; If we can't pass every return value in registers, we will pass everything38; in memroy. The caller provides space for the return value and passes39; the address in %r2. The first input argument will be in %r3.40; CHECK-LABEL: test2:41; CHECK: lr %r3, %r242; CHECK-DAG: la %r2, 160(%r15)43; CHECK: brasl %r14, gen244; CHECK: l %r2, 160(%r15)45; CHECK: a %r2, 164(%r15)46; CHECK: a %r2, 168(%r15)47; CHECK: a %r2, 172(%r15)48; CHECK: a %r2, 176(%r15)49; CHECK-O0-LABEL: test2:50; CHECK-O0: st %r2, [[SPILL1:[0-9]+]](%r15)51; CHECK-O0: l %r3, [[SPILL1]](%r15)52; CHECK-O0: la %r2, 160(%r15)53; CHECK-O0: brasl %r14, gen254; CHECK-O0-DAG: l %r{{.*}}, 176(%r15)55; CHECK-O0-DAG: l %r{{.*}}, 172(%r15)56; CHECK-O0-DAG: l %r{{.*}}, 168(%r15)57; CHECK-O0-DAG: l %r{{.*}}, 164(%r15)58; CHECK-O0-DAG: l %r{{.*}}, 160(%r15)59; CHECK-O0: ar60; CHECK-O0: ar61; CHECK-O0: ar62; CHECK-O0: ar63define i32 @test2(i32 %key) #0 {64entry:65 %key.addr = alloca i32, align 466 store i32 %key, ptr %key.addr, align 467 %0 = load i32, ptr %key.addr, align 468 %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0)69 70 %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 071 %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 172 %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 273 %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 374 %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 475 76 %add = add nsw i32 %v3, %v577 %add1 = add nsw i32 %add, %v678 %add2 = add nsw i32 %add1, %v779 %add3 = add nsw i32 %add2, %v880 ret i32 %add381}82 83; The address of the return value is passed in %r2.84; On return, %r2 will contain the adddress that has been passed in by the caller in %r2.85; CHECK-LABEL: gen2:86; CHECK: st %r3, 16(%r2)87; CHECK: st %r3, 12(%r2)88; CHECK: st %r3, 8(%r2)89; CHECK: st %r3, 4(%r2)90; CHECK: st %r3, 0(%r2)91; CHECK-O0-LABEL: gen2:92; CHECK-O0-DAG: st %r3, 16(%r2)93; CHECK-O0-DAG: st %r3, 12(%r2)94; CHECK-O0-DAG: st %r3, 8(%r2)95; CHECK-O0-DAG: st %r3, 4(%r2)96; CHECK-O0-DAG: st %r3, 0(%r2)97define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {98 %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 099 %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1100 %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2101 %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3102 %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4103 ret { i32, i32, i32, i32, i32 } %Z4104}105 106; The return value {i32, i32, i32, i32} will be returned via registers107; %r2, %r3, %r4, %r5.108; CHECK-LABEL: test3:109; CHECK: brasl %r14, gen3110; CHECK: ar %r2, %r3111; CHECK: ar %r2, %r4112; CHECK: ar %r2, %r5113; CHECK-O0-LABEL: test3:114; CHECK-O0: brasl %r14, gen3115; CHECK-O0: ar %r2, %r3116; CHECK-O0: ar %r2, %r4117; CHECK-O0: ar %r2, %r5118define i32 @test3(i32 %key) #0 {119entry:120 %key.addr = alloca i32, align 4121 store i32 %key, ptr %key.addr, align 4122 %0 = load i32, ptr %key.addr, align 4123 %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0)124 125 %v3 = extractvalue { i32, i32, i32, i32 } %call, 0126 %v5 = extractvalue { i32, i32, i32, i32 } %call, 1127 %v6 = extractvalue { i32, i32, i32, i32 } %call, 2128 %v7 = extractvalue { i32, i32, i32, i32 } %call, 3129 130 %add = add nsw i32 %v3, %v5131 %add1 = add nsw i32 %add, %v6132 %add2 = add nsw i32 %add1, %v7133 ret i32 %add2134}135 136declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)137 138; The return value {float, float, float, float} will be returned via registers139; %f0, %f2, %f4, %f6.140; CHECK-LABEL: test4:141; CHECK: brasl %r14, gen4142; CHECK: aebr %f0, %f2143; CHECK: aebr %f0, %f4144; CHECK: aebr %f0, %f6145; CHECK-O0-LABEL: test4:146; CHECK-O0: brasl %r14, gen4147; CHECK-O0: aebr %f0, %f2148; CHECK-O0: aebr %f0, %f4149; CHECK-O0: aebr %f0, %f6150define float @test4(float %key) #0 {151entry:152 %key.addr = alloca float, align 4153 store float %key, ptr %key.addr, align 4154 %0 = load float, ptr %key.addr, align 4155 %call = call swiftcc { float, float, float, float } @gen4(float %0)156 157 %v3 = extractvalue { float, float, float, float } %call, 0158 %v5 = extractvalue { float, float, float, float } %call, 1159 %v6 = extractvalue { float, float, float, float } %call, 2160 %v7 = extractvalue { float, float, float, float } %call, 3161 162 %add = fadd float %v3, %v5163 %add1 = fadd float %add, %v6164 %add2 = fadd float %add1, %v7165 ret float %add2166}167 168declare swiftcc { float, float, float, float } @gen4(float %key)169 170; CHECK-LABEL: consume_i1_ret:171; CHECK: brasl %r14, produce_i1_ret172; CHECK: nilf %r2, 1173; CHECK: nilf %r3, 1174; CHECK: nilf %r4, 1175; CHECK: nilf %r5, 1176; CHECK-O0-LABEL: consume_i1_ret:177; CHECK-O0: brasl %r14, produce_i1_ret178; CHECK-O0: nilf %r2, 1179; CHECK-O0: nilf %r3, 1180; CHECK-O0: nilf %r4, 1181; CHECK-O0: nilf %r5, 1182define void @consume_i1_ret() {183 %call = call swiftcc { i1, i1, i1, i1 } @produce_i1_ret()184 %v3 = extractvalue { i1, i1, i1, i1 } %call, 0185 %v5 = extractvalue { i1, i1, i1, i1 } %call, 1186 %v6 = extractvalue { i1, i1, i1, i1 } %call, 2187 %v7 = extractvalue { i1, i1, i1, i1 } %call, 3188 %val = zext i1 %v3 to i32189 store volatile i32 %val, ptr @var190 %val2 = zext i1 %v5 to i32191 store volatile i32 %val2, ptr @var192 %val3 = zext i1 %v6 to i32193 store volatile i32 %val3, ptr @var194 %val4 = zext i1 %v7 to i32195 store i32 %val4, ptr @var196 ret void197}198 199declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret()200