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1; Test load-and-trap instructions (LAT/LGAT)2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s4 5declare void @llvm.trap()6 7; Check LAT with no displacement.8define i32 @f1(ptr %ptr) {9; CHECK-LABEL: f1:10; CHECK: lat %r2, 0(%r2)11; CHECK: br %r1412entry:13 %val = load i32, ptr %ptr14 %cmp = icmp eq i32 %val, 015 br i1 %cmp, label %if.then, label %if.end16 17if.then: ; preds = %entry18 tail call void @llvm.trap()19 unreachable20 21if.end: ; preds = %entry22 ret i32 %val23}24 25; Check the high end of the LAT range.26define i32 @f2(ptr %src) {27; CHECK-LABEL: f2:28; CHECK: lat %r2, 524284(%r2)29; CHECK: br %r1430 %ptr = getelementptr i32, ptr %src, i64 13107131 %val = load i32, ptr %ptr32 %cmp = icmp eq i32 %val, 033 br i1 %cmp, label %if.then, label %if.end34 35if.then: ; preds = %entry36 tail call void @llvm.trap()37 unreachable38 39if.end: ; preds = %entry40 ret i32 %val41}42 43; Check the next word up, which needs separate address logic.44; Other sequences besides this one would be OK.45define i32 @f3(ptr %src) {46; CHECK-LABEL: f3:47; CHECK: agfi %r2, 52428848; CHECK: lat %r2, 0(%r2)49; CHECK: br %r1450 %ptr = getelementptr i32, ptr %src, i64 13107251 %val = load i32, ptr %ptr52 %cmp = icmp eq i32 %val, 053 br i1 %cmp, label %if.then, label %if.end54 55if.then: ; preds = %entry56 tail call void @llvm.trap()57 unreachable58 59if.end: ; preds = %entry60 ret i32 %val61}62 63; Check that LAT allows an index.64define i32 @f4(i64 %src, i64 %index) {65; CHECK-LABEL: f4:66; CHECK: lat %r2, 524287(%r3,%r2)67; CHECK: br %r1468 %add1 = add i64 %src, %index69 %add2 = add i64 %add1, 52428770 %ptr = inttoptr i64 %add2 to ptr71 %val = load i32, ptr %ptr72 %cmp = icmp eq i32 %val, 073 br i1 %cmp, label %if.then, label %if.end74 75if.then: ; preds = %entry76 tail call void @llvm.trap()77 unreachable78 79if.end: ; preds = %entry80 ret i32 %val81}82 83; Check LGAT with no displacement.84define i64 @f5(ptr %ptr) {85; CHECK-LABEL: f5:86; CHECK: lgat %r2, 0(%r2)87; CHECK: br %r1488entry:89 %val = load i64, ptr %ptr90 %cmp = icmp eq i64 %val, 091 br i1 %cmp, label %if.then, label %if.end92 93if.then: ; preds = %entry94 tail call void @llvm.trap()95 unreachable96 97if.end: ; preds = %entry98 ret i64 %val99}100 101; Check the high end of the LGAT range.102define i64 @f6(ptr %src) {103; CHECK-LABEL: f6:104; CHECK: lgat %r2, 524280(%r2)105; CHECK: br %r14106 %ptr = getelementptr i64, ptr %src, i64 65535107 %val = load i64, ptr %ptr108 %cmp = icmp eq i64 %val, 0109 br i1 %cmp, label %if.then, label %if.end110 111if.then: ; preds = %entry112 tail call void @llvm.trap()113 unreachable114 115if.end: ; preds = %entry116 ret i64 %val117}118 119; Check the next word up, which needs separate address logic.120; Other sequences besides this one would be OK.121define i64 @f7(ptr %src) {122; CHECK-LABEL: f7:123; CHECK: agfi %r2, 524288124; CHECK: lgat %r2, 0(%r2)125; CHECK: br %r14126 %ptr = getelementptr i64, ptr %src, i64 65536127 %val = load i64, ptr %ptr128 %cmp = icmp eq i64 %val, 0129 br i1 %cmp, label %if.then, label %if.end130 131if.then: ; preds = %entry132 tail call void @llvm.trap()133 unreachable134 135if.end: ; preds = %entry136 ret i64 %val137}138 139; Check that LGAT allows an index.140define i64 @f8(i64 %src, i64 %index) {141; CHECK-LABEL: f8:142; CHECK: lgat %r2, 524287(%r3,%r2)143; CHECK: br %r14144 %add1 = add i64 %src, %index145 %add2 = add i64 %add1, 524287146 %ptr = inttoptr i64 %add2 to ptr147 %val = load i64, ptr %ptr148 %cmp = icmp eq i64 %val, 0149 br i1 %cmp, label %if.then, label %if.end150 151if.then: ; preds = %entry152 tail call void @llvm.trap()153 unreachable154 155if.end: ; preds = %entry156 ret i64 %val157}158