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1; Test load-and-trap instructions (LLGFAT/LLGFTAT)2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s4 5declare void @llvm.trap()6 7; Check LLGFAT with no displacement.8define i64 @f1(ptr %ptr) {9; CHECK-LABEL: f1:10; CHECK: llgfat %r2, 0(%r2)11; CHECK: br %r1412entry:13 %val = load i32, ptr %ptr14 %ext = zext i32 %val to i6415 %cmp = icmp eq i64 %ext, 016 br i1 %cmp, label %if.then, label %if.end17 18if.then: ; preds = %entry19 tail call void @llvm.trap()20 unreachable21 22if.end: ; preds = %entry23 ret i64 %ext24}25 26; Check the high end of the LLGFAT range.27define i64 @f2(ptr %src) {28; CHECK-LABEL: f2:29; CHECK: llgfat %r2, 524284(%r2)30; CHECK: br %r1431 %ptr = getelementptr i32, ptr %src, i64 13107132 %val = load i32, ptr %ptr33 %ext = zext i32 %val to i6434 %cmp = icmp eq i64 %ext, 035 br i1 %cmp, label %if.then, label %if.end36 37if.then: ; preds = %entry38 tail call void @llvm.trap()39 unreachable40 41if.end: ; preds = %entry42 ret i64 %ext43}44 45; Check the next word up, which needs separate address logic.46; Other sequences besides this one would be OK.47define i64 @f3(ptr %src) {48; CHECK-LABEL: f3:49; CHECK: agfi %r2, 52428850; CHECK: llgfat %r2, 0(%r2)51; CHECK: br %r1452 %ptr = getelementptr i32, ptr %src, i64 13107253 %val = load i32, ptr %ptr54 %ext = zext i32 %val to i6455 %cmp = icmp eq i64 %ext, 056 br i1 %cmp, label %if.then, label %if.end57 58if.then: ; preds = %entry59 tail call void @llvm.trap()60 unreachable61 62if.end: ; preds = %entry63 ret i64 %ext64}65 66; Check that LLGFAT allows an index.67define i64 @f4(i64 %src, i64 %index) {68; CHECK-LABEL: f4:69; CHECK: llgfat %r2, 524287(%r3,%r2)70; CHECK: br %r1471 %add1 = add i64 %src, %index72 %add2 = add i64 %add1, 52428773 %ptr = inttoptr i64 %add2 to ptr74 %val = load i32, ptr %ptr75 %ext = zext i32 %val to i6476 %cmp = icmp eq i64 %ext, 077 br i1 %cmp, label %if.then, label %if.end78 79if.then: ; preds = %entry80 tail call void @llvm.trap()81 unreachable82 83if.end: ; preds = %entry84 ret i64 %ext85}86 87; Check LLGTAT with no displacement.88define i64 @f5(ptr %ptr) {89; CHECK-LABEL: f5:90; CHECK: llgtat %r2, 0(%r2)91; CHECK: br %r1492entry:93 %val = load i32, ptr %ptr94 %ext = zext i32 %val to i6495 %and = and i64 %ext, 214748364796 %cmp = icmp eq i64 %and, 097 br i1 %cmp, label %if.then, label %if.end98 99if.then: ; preds = %entry100 tail call void @llvm.trap()101 unreachable102 103if.end: ; preds = %entry104 ret i64 %and105}106 107; Check the high end of the LLGTAT range.108define i64 @f6(ptr %src) {109; CHECK-LABEL: f6:110; CHECK: llgtat %r2, 524284(%r2)111; CHECK: br %r14112 %ptr = getelementptr i32, ptr %src, i64 131071113 %val = load i32, ptr %ptr114 %ext = zext i32 %val to i64115 %and = and i64 %ext, 2147483647116 %cmp = icmp eq i64 %and, 0117 br i1 %cmp, label %if.then, label %if.end118 119if.then: ; preds = %entry120 tail call void @llvm.trap()121 unreachable122 123if.end: ; preds = %entry124 ret i64 %and125}126 127; Check the next word up, which needs separate address logic.128; Other sequences besides this one would be OK.129define i64 @f7(ptr %src) {130; CHECK-LABEL: f7:131; CHECK: agfi %r2, 524288132; CHECK: llgtat %r2, 0(%r2)133; CHECK: br %r14134 %ptr = getelementptr i32, ptr %src, i64 131072135 %val = load i32, ptr %ptr136 %ext = zext i32 %val to i64137 %and = and i64 %ext, 2147483647138 %cmp = icmp eq i64 %and, 0139 br i1 %cmp, label %if.then, label %if.end140 141if.then: ; preds = %entry142 tail call void @llvm.trap()143 unreachable144 145if.end: ; preds = %entry146 ret i64 %and147}148 149; Check that LLGTAT allows an index.150define i64 @f8(i64 %src, i64 %index) {151; CHECK-LABEL: f8:152; CHECK: llgtat %r2, 524287(%r3,%r2)153; CHECK: br %r14154 %add1 = add i64 %src, %index155 %add2 = add i64 %add1, 524287156 %ptr = inttoptr i64 %add2 to ptr157 %val = load i32, ptr %ptr158 %ext = zext i32 %val to i64159 %and = and i64 %ext, 2147483647160 %cmp = icmp eq i64 %and, 0161 br i1 %cmp, label %if.then, label %if.end162 163if.then: ; preds = %entry164 tail call void @llvm.trap()165 unreachable166 167if.end: ; preds = %entry168 ret i64 %and169}170 171