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1; Test v16i8 absolute.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test with slt.6define <16 x i8> @f1(<16 x i8> %val) {7; CHECK-LABEL: f1:8; CHECK: vlpb %v24, %v249; CHECK: br %r1410 %cmp = icmp slt <16 x i8> %val, zeroinitializer11 %neg = sub <16 x i8> zeroinitializer, %val12 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val13 ret <16 x i8> %ret14}15 16; Test with sle.17define <16 x i8> @f2(<16 x i8> %val) {18; CHECK-LABEL: f2:19; CHECK: vlpb %v24, %v2420; CHECK: br %r1421 %cmp = icmp sle <16 x i8> %val, zeroinitializer22 %neg = sub <16 x i8> zeroinitializer, %val23 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val24 ret <16 x i8> %ret25}26 27; Test with sgt.28define <16 x i8> @f3(<16 x i8> %val) {29; CHECK-LABEL: f3:30; CHECK: vlpb %v24, %v2431; CHECK: br %r1432 %cmp = icmp sgt <16 x i8> %val, zeroinitializer33 %neg = sub <16 x i8> zeroinitializer, %val34 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg35 ret <16 x i8> %ret36}37 38; Test with sge.39define <16 x i8> @f4(<16 x i8> %val) {40; CHECK-LABEL: f4:41; CHECK: vlpb %v24, %v2442; CHECK: br %r1443 %cmp = icmp sge <16 x i8> %val, zeroinitializer44 %neg = sub <16 x i8> zeroinitializer, %val45 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg46 ret <16 x i8> %ret47}48 49; Test that negative absolute uses VLPB too. There is no vector equivalent50; of LOAD NEGATIVE.51define <16 x i8> @f5(<16 x i8> %val) {52; CHECK-LABEL: f5:53; CHECK: vlpb [[REG:%v[0-9]+]], %v2454; CHECK: vlcb %v24, [[REG]]55; CHECK: br %r1456 %cmp = icmp slt <16 x i8> %val, zeroinitializer57 %neg = sub <16 x i8> zeroinitializer, %val58 %abs = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val59 %ret = sub <16 x i8> zeroinitializer, %abs60 ret <16 x i8> %ret61}62 63; Try another form of negative absolute (slt version).64define <16 x i8> @f6(<16 x i8> %val) {65; CHECK-LABEL: f6:66; CHECK: vlpb [[REG:%v[0-9]+]], %v2467; CHECK: vlcb %v24, [[REG]]68; CHECK: br %r1469 %cmp = icmp slt <16 x i8> %val, zeroinitializer70 %neg = sub <16 x i8> zeroinitializer, %val71 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg72 ret <16 x i8> %ret73}74 75; Test with sle.76define <16 x i8> @f7(<16 x i8> %val) {77; CHECK-LABEL: f7:78; CHECK: vlpb [[REG:%v[0-9]+]], %v2479; CHECK: vlcb %v24, [[REG]]80; CHECK: br %r1481 %cmp = icmp sle <16 x i8> %val, zeroinitializer82 %neg = sub <16 x i8> zeroinitializer, %val83 %ret = select <16 x i1> %cmp, <16 x i8> %val, <16 x i8> %neg84 ret <16 x i8> %ret85}86 87; Test with sgt.88define <16 x i8> @f8(<16 x i8> %val) {89; CHECK-LABEL: f8:90; CHECK: vlpb [[REG:%v[0-9]+]], %v2491; CHECK: vlcb %v24, [[REG]]92; CHECK: br %r1493 %cmp = icmp sgt <16 x i8> %val, zeroinitializer94 %neg = sub <16 x i8> zeroinitializer, %val95 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val96 ret <16 x i8> %ret97}98 99; Test with sge.100define <16 x i8> @f9(<16 x i8> %val) {101; CHECK-LABEL: f9:102; CHECK: vlpb [[REG:%v[0-9]+]], %v24103; CHECK: vlcb %v24, [[REG]]104; CHECK: br %r14105 %cmp = icmp sge <16 x i8> %val, zeroinitializer106 %neg = sub <16 x i8> zeroinitializer, %val107 %ret = select <16 x i1> %cmp, <16 x i8> %neg, <16 x i8> %val108 ret <16 x i8> %ret109}110 111; Test with an SRA-based boolean vector.112define <16 x i8> @f10(<16 x i8> %val) {113; CHECK-LABEL: f10:114; CHECK: vlpb %v24, %v24115; CHECK: br %r14116 %shr = ashr <16 x i8> %val,117 <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,118 i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>119 %neg = sub <16 x i8> zeroinitializer, %val120 %and1 = and <16 x i8> %shr, %neg121 %not = xor <16 x i8> %shr,122 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,123 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>124 %and2 = and <16 x i8> %not, %val125 %ret = or <16 x i8> %and1, %and2126 ret <16 x i8> %ret127}128 129; ...and again in reverse130define <16 x i8> @f11(<16 x i8> %val) {131; CHECK-LABEL: f11:132; CHECK: vlpb [[REG:%v[0-9]+]], %v24133; CHECK: vlcb %v24, [[REG]]134; CHECK: br %r14135 %shr = ashr <16 x i8> %val,136 <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,137 i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>138 %and1 = and <16 x i8> %shr, %val139 %not = xor <16 x i8> %shr,140 <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,141 i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>142 %neg = sub <16 x i8> zeroinitializer, %val143 %and2 = and <16 x i8> %not, %neg144 %ret = or <16 x i8> %and1, %and2145 ret <16 x i8> %ret146}147