114 lines · plain
1; Test vector zero extensions, which need to be implemented as ANDs.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test a v16i1->v16i8 extension.6define <16 x i8> @f1(<16 x i8> %val) {7; CHECK-LABEL: f1:8; CHECK: vrepib [[REG:%v[0-9]+]], 19; CHECK: vn %v24, %v24, [[REG]]10; CHECK: br %r1411 %trunc = trunc <16 x i8> %val to <16 x i1>12 %ret = zext <16 x i1> %trunc to <16 x i8>13 ret <16 x i8> %ret14}15 16; Test a v8i1->v8i16 extension.17define <8 x i16> @f2(<8 x i16> %val) {18; CHECK-LABEL: f2:19; CHECK: vrepih [[REG:%v[0-9]+]], 120; CHECK: vn %v24, %v24, [[REG]]21; CHECK: br %r1422 %trunc = trunc <8 x i16> %val to <8 x i1>23 %ret = zext <8 x i1> %trunc to <8 x i16>24 ret <8 x i16> %ret25}26 27; Test a v8i8->v8i16 extension.28define <8 x i16> @f3(<8 x i16> %val) {29; CHECK-LABEL: f3:30; CHECK: vgbm [[REG:%v[0-9]+]], 2184531; CHECK: vn %v24, %v24, [[REG]]32; CHECK: br %r1433 %trunc = trunc <8 x i16> %val to <8 x i8>34 %ret = zext <8 x i8> %trunc to <8 x i16>35 ret <8 x i16> %ret36}37 38; Test a v4i1->v4i32 extension.39define <4 x i32> @f4(<4 x i32> %val) {40; CHECK-LABEL: f4:41; CHECK: vrepif [[REG:%v[0-9]+]], 142; CHECK: vn %v24, %v24, [[REG]]43; CHECK: br %r1444 %trunc = trunc <4 x i32> %val to <4 x i1>45 %ret = zext <4 x i1> %trunc to <4 x i32>46 ret <4 x i32> %ret47}48 49; Test a v4i8->v4i32 extension.50define <4 x i32> @f5(<4 x i32> %val) {51; CHECK-LABEL: f5:52; CHECK: vgbm [[REG:%v[0-9]+]], 436953; CHECK: vn %v24, %v24, [[REG]]54; CHECK: br %r1455 %trunc = trunc <4 x i32> %val to <4 x i8>56 %ret = zext <4 x i8> %trunc to <4 x i32>57 ret <4 x i32> %ret58}59 60; Test a v4i16->v4i32 extension.61define <4 x i32> @f6(<4 x i32> %val) {62; CHECK-LABEL: f6:63; CHECK: vgbm [[REG:%v[0-9]+]], 1310764; CHECK: vn %v24, %v24, [[REG]]65; CHECK: br %r1466 %trunc = trunc <4 x i32> %val to <4 x i16>67 %ret = zext <4 x i16> %trunc to <4 x i32>68 ret <4 x i32> %ret69}70 71; Test a v2i1->v2i64 extension.72define <2 x i64> @f7(<2 x i64> %val) {73; CHECK-LABEL: f7:74; CHECK: vrepig [[REG:%v[0-9]+]], 175; CHECK: vn %v24, %v24, [[REG]]76; CHECK: br %r1477 %trunc = trunc <2 x i64> %val to <2 x i1>78 %ret = zext <2 x i1> %trunc to <2 x i64>79 ret <2 x i64> %ret80}81 82; Test a v2i8->v2i64 extension.83define <2 x i64> @f8(<2 x i64> %val) {84; CHECK-LABEL: f8:85; CHECK: vgbm [[REG:%v[0-9]+]], 25786; CHECK: vn %v24, %v24, [[REG]]87; CHECK: br %r1488 %trunc = trunc <2 x i64> %val to <2 x i8>89 %ret = zext <2 x i8> %trunc to <2 x i64>90 ret <2 x i64> %ret91}92 93; Test a v2i16->v2i64 extension.94define <2 x i64> @f9(<2 x i64> %val) {95; CHECK-LABEL: f9:96; CHECK: vgbm [[REG:%v[0-9]+]], 77197; CHECK: vn %v24, %v24, [[REG]]98; CHECK: br %r1499 %trunc = trunc <2 x i64> %val to <2 x i16>100 %ret = zext <2 x i16> %trunc to <2 x i64>101 ret <2 x i64> %ret102}103 104; Test a v2i32->v2i64 extension.105define <2 x i64> @f10(<2 x i64> %val) {106; CHECK-LABEL: f10:107; CHECK: vgbm [[REG:%v[0-9]+]], 3855108; CHECK: vn %v24, %v24, [[REG]]109; CHECK: br %r14110 %trunc = trunc <2 x i64> %val to <2 x i32>111 %ret = zext <2 x i32> %trunc to <2 x i64>112 ret <2 x i64> %ret113}114