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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test the handling of unnamed vector arguments.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK6 7; This routine is called with two named vector argument (passed8; in %v24 and %v26) and two unnamed vector arguments (passed9; in the double-wide stack slots at 160 and 176).10declare void @bar(<4 x i32>, <4 x i32>, ...)11 12define void @foo() {13; CHECK-VEC-LABEL: foo:14; CHECK-VEC:       # %bb.0:15; CHECK-VEC-NEXT:    stmg %r14, %r15, 112(%r15)16; CHECK-VEC-NEXT:    .cfi_offset %r14, -4817; CHECK-VEC-NEXT:    .cfi_offset %r15, -4018; CHECK-VEC-NEXT:    aghi %r15, -19219; CHECK-VEC-NEXT:    .cfi_def_cfa_offset 35220; CHECK-VEC-NEXT:    vrepif %v0, 421; CHECK-VEC-NEXT:    vst %v0, 176(%r15), 322; CHECK-VEC-NEXT:    vrepif %v0, 323; CHECK-VEC-NEXT:    vrepif %v24, 124; CHECK-VEC-NEXT:    vrepif %v26, 225; CHECK-VEC-NEXT:    vst %v0, 160(%r15), 326; CHECK-VEC-NEXT:    brasl %r14, bar@PLT27; CHECK-VEC-NEXT:    lmg %r14, %r15, 304(%r15)28; CHECK-VEC-NEXT:    br %r1429;30; CHECK-STACK-LABEL: foo:31; CHECK-STACK:       # %bb.0:32; CHECK-STACK-NEXT:    stmg %r14, %r15, 112(%r15)33; CHECK-STACK-NEXT:    .cfi_offset %r14, -4834; CHECK-STACK-NEXT:    .cfi_offset %r15, -4035; CHECK-STACK-NEXT:    aghi %r15, -19236; CHECK-STACK-NEXT:    .cfi_def_cfa_offset 35237; CHECK-STACK-NEXT:    vrepif %v0, 438; CHECK-STACK-NEXT:    vst %v0, 176(%r15), 339; CHECK-STACK-NEXT:    vrepif %v0, 340; CHECK-STACK-NEXT:    vrepif %v24, 141; CHECK-STACK-NEXT:    vrepif %v26, 242; CHECK-STACK-NEXT:    vst %v0, 160(%r15), 343; CHECK-STACK-NEXT:    brasl %r14, bar@PLT44; CHECK-STACK-NEXT:    lmg %r14, %r15, 304(%r15)45; CHECK-STACK-NEXT:    br %r1446 47  call void (<4 x i32>, <4 x i32>, ...) @bar48              (<4 x i32> <i32 1, i32 1, i32 1, i32 1>,49               <4 x i32> <i32 2, i32 2, i32 2, i32 2>,50               <4 x i32> <i32 3, i32 3, i32 3, i32 3>,51               <4 x i32> <i32 4, i32 4, i32 4, i32 4>)52  ret void53}54