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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; Test loads of byte-swapped vector elements.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s5 6declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)7declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)8declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)9 10; Test v8i16 loads.11define <8 x i16> @f1(ptr %ptr) {12; CHECK-LABEL: f1:13; CHECK: # %bb.0:14; CHECK-NEXT: vlbrh %v24, 0(%r2)15; CHECK-NEXT: br %r1416 %load = load <8 x i16>, ptr %ptr17 %ret = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %load)18 ret <8 x i16> %ret19}20 21; Test v4i32 loads.22define <4 x i32> @f2(ptr %ptr) {23; CHECK-LABEL: f2:24; CHECK: # %bb.0:25; CHECK-NEXT: vlbrf %v24, 0(%r2)26; CHECK-NEXT: br %r1427 %load = load <4 x i32>, ptr %ptr28 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)29 ret <4 x i32> %ret30}31 32; Test v2i64 loads.33define <2 x i64> @f3(ptr %ptr) {34; CHECK-LABEL: f3:35; CHECK: # %bb.0:36; CHECK-NEXT: vlbrg %v24, 0(%r2)37; CHECK-NEXT: br %r1438 %load = load <2 x i64>, ptr %ptr39 %ret = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %load)40 ret <2 x i64> %ret41}42 43; Test the highest aligned in-range offset.44define <4 x i32> @f4(ptr %base) {45; CHECK-LABEL: f4:46; CHECK: # %bb.0:47; CHECK-NEXT: vlbrf %v24, 4080(%r2)48; CHECK-NEXT: br %r1449 %ptr = getelementptr <4 x i32>, ptr %base, i64 25550 %load = load <4 x i32>, ptr %ptr51 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)52 ret <4 x i32> %ret53}54 55; Test the highest unaligned in-range offset.56define <4 x i32> @f5(ptr %base) {57; CHECK-LABEL: f5:58; CHECK: # %bb.0:59; CHECK-NEXT: vlbrf %v24, 4095(%r2)60; CHECK-NEXT: br %r1461 %addr = getelementptr i8, ptr %base, i64 409562 %load = load <4 x i32>, ptr %addr63 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)64 ret <4 x i32> %ret65}66 67; Test the next offset up, which requires separate address logic,68define <4 x i32> @f6(ptr %base) {69; CHECK-LABEL: f6:70; CHECK: # %bb.0:71; CHECK-NEXT: aghi %r2, 409672; CHECK-NEXT: vlbrf %v24, 0(%r2)73; CHECK-NEXT: br %r1474 %ptr = getelementptr <4 x i32>, ptr %base, i64 25675 %load = load <4 x i32>, ptr %ptr76 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)77 ret <4 x i32> %ret78}79 80; Test negative offsets, which also require separate address logic,81define <4 x i32> @f7(ptr %base) {82; CHECK-LABEL: f7:83; CHECK: # %bb.0:84; CHECK-NEXT: aghi %r2, -1685; CHECK-NEXT: vlbrf %v24, 0(%r2)86; CHECK-NEXT: br %r1487 %ptr = getelementptr <4 x i32>, ptr %base, i64 -188 %load = load <4 x i32>, ptr %ptr89 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)90 ret <4 x i32> %ret91}92 93; Check that indexes are allowed.94define <4 x i32> @f8(ptr %base, i64 %index) {95; CHECK-LABEL: f8:96; CHECK: # %bb.0:97; CHECK-NEXT: vlbrf %v24, 0(%r3,%r2)98; CHECK-NEXT: br %r1499 %addr = getelementptr i8, ptr %base, i64 %index100 %load = load <4 x i32>, ptr %addr101 %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %load)102 ret <4 x i32> %ret103}104 105