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1; Test v8i16 comparisons.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test eq.6define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {7; CHECK-LABEL: f1:8; CHECK: vceqh %v24, %v26, %v289; CHECK-NEXT: br %r1410 %cmp = icmp eq <8 x i16> %val1, %val211 %ret = sext <8 x i1> %cmp to <8 x i16>12 ret <8 x i16> %ret13}14 15; Test ne.16define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {17; CHECK-LABEL: f2:18; CHECK: vceqh [[REG:%v[0-9]+]], %v26, %v2819; CHECK-NEXT: vno %v24, [[REG]], [[REG]]20; CHECK-NEXT: br %r1421 %cmp = icmp ne <8 x i16> %val1, %val222 %ret = sext <8 x i1> %cmp to <8 x i16>23 ret <8 x i16> %ret24}25 26; Test sgt.27define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {28; CHECK-LABEL: f3:29; CHECK: vchh %v24, %v26, %v2830; CHECK-NEXT: br %r1431 %cmp = icmp sgt <8 x i16> %val1, %val232 %ret = sext <8 x i1> %cmp to <8 x i16>33 ret <8 x i16> %ret34}35 36; Test sge.37define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {38; CHECK-LABEL: f4:39; CHECK: vchh [[REG:%v[0-9]+]], %v28, %v2640; CHECK-NEXT: vno %v24, [[REG]], [[REG]]41; CHECK-NEXT: br %r1442 %cmp = icmp sge <8 x i16> %val1, %val243 %ret = sext <8 x i1> %cmp to <8 x i16>44 ret <8 x i16> %ret45}46 47; Test sle.48define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {49; CHECK-LABEL: f5:50; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v2851; CHECK-NEXT: vno %v24, [[REG]], [[REG]]52; CHECK-NEXT: br %r1453 %cmp = icmp sle <8 x i16> %val1, %val254 %ret = sext <8 x i1> %cmp to <8 x i16>55 ret <8 x i16> %ret56}57 58; Test slt.59define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {60; CHECK-LABEL: f6:61; CHECK: vchh %v24, %v28, %v2662; CHECK-NEXT: br %r1463 %cmp = icmp slt <8 x i16> %val1, %val264 %ret = sext <8 x i1> %cmp to <8 x i16>65 ret <8 x i16> %ret66}67 68; Test ugt.69define <8 x i16> @f7(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {70; CHECK-LABEL: f7:71; CHECK: vchlh %v24, %v26, %v2872; CHECK-NEXT: br %r1473 %cmp = icmp ugt <8 x i16> %val1, %val274 %ret = sext <8 x i1> %cmp to <8 x i16>75 ret <8 x i16> %ret76}77 78; Test uge.79define <8 x i16> @f8(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {80; CHECK-LABEL: f8:81; CHECK: vchlh [[REG:%v[0-9]+]], %v28, %v2682; CHECK-NEXT: vno %v24, [[REG]], [[REG]]83; CHECK-NEXT: br %r1484 %cmp = icmp uge <8 x i16> %val1, %val285 %ret = sext <8 x i1> %cmp to <8 x i16>86 ret <8 x i16> %ret87}88 89; Test ule.90define <8 x i16> @f9(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {91; CHECK-LABEL: f9:92; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v2893; CHECK-NEXT: vno %v24, [[REG]], [[REG]]94; CHECK-NEXT: br %r1495 %cmp = icmp ule <8 x i16> %val1, %val296 %ret = sext <8 x i1> %cmp to <8 x i16>97 ret <8 x i16> %ret98}99 100; Test ult.101define <8 x i16> @f10(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {102; CHECK-LABEL: f10:103; CHECK: vchlh %v24, %v28, %v26104; CHECK-NEXT: br %r14105 %cmp = icmp ult <8 x i16> %val1, %val2106 %ret = sext <8 x i1> %cmp to <8 x i16>107 ret <8 x i16> %ret108}109 110; Test eq selects.111define <8 x i16> @f11(<8 x i16> %val1, <8 x i16> %val2,112 <8 x i16> %val3, <8 x i16> %val4) {113; CHECK-LABEL: f11:114; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26115; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]116; CHECK-NEXT: br %r14117 %cmp = icmp eq <8 x i16> %val1, %val2118 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4119 ret <8 x i16> %ret120}121 122; Test ne selects.123define <8 x i16> @f12(<8 x i16> %val1, <8 x i16> %val2,124 <8 x i16> %val3, <8 x i16> %val4) {125; CHECK-LABEL: f12:126; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26127; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]128; CHECK-NEXT: br %r14129 %cmp = icmp ne <8 x i16> %val1, %val2130 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4131 ret <8 x i16> %ret132}133 134; Test sgt selects.135define <8 x i16> @f13(<8 x i16> %val1, <8 x i16> %val2,136 <8 x i16> %val3, <8 x i16> %val4) {137; CHECK-LABEL: f13:138; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26139; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]140; CHECK-NEXT: br %r14141 %cmp = icmp sgt <8 x i16> %val1, %val2142 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4143 ret <8 x i16> %ret144}145 146; Test sge selects.147define <8 x i16> @f14(<8 x i16> %val1, <8 x i16> %val2,148 <8 x i16> %val3, <8 x i16> %val4) {149; CHECK-LABEL: f14:150; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24151; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]152; CHECK-NEXT: br %r14153 %cmp = icmp sge <8 x i16> %val1, %val2154 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4155 ret <8 x i16> %ret156}157 158; Test sle selects.159define <8 x i16> @f15(<8 x i16> %val1, <8 x i16> %val2,160 <8 x i16> %val3, <8 x i16> %val4) {161; CHECK-LABEL: f15:162; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26163; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]164; CHECK-NEXT: br %r14165 %cmp = icmp sle <8 x i16> %val1, %val2166 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4167 ret <8 x i16> %ret168}169 170; Test slt selects.171define <8 x i16> @f16(<8 x i16> %val1, <8 x i16> %val2,172 <8 x i16> %val3, <8 x i16> %val4) {173; CHECK-LABEL: f16:174; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24175; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]176; CHECK-NEXT: br %r14177 %cmp = icmp slt <8 x i16> %val1, %val2178 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4179 ret <8 x i16> %ret180}181 182; Test ugt selects.183define <8 x i16> @f17(<8 x i16> %val1, <8 x i16> %val2,184 <8 x i16> %val3, <8 x i16> %val4) {185; CHECK-LABEL: f17:186; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26187; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]188; CHECK-NEXT: br %r14189 %cmp = icmp ugt <8 x i16> %val1, %val2190 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4191 ret <8 x i16> %ret192}193 194; Test uge selects.195define <8 x i16> @f18(<8 x i16> %val1, <8 x i16> %val2,196 <8 x i16> %val3, <8 x i16> %val4) {197; CHECK-LABEL: f18:198; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24199; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]200; CHECK-NEXT: br %r14201 %cmp = icmp uge <8 x i16> %val1, %val2202 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4203 ret <8 x i16> %ret204}205 206; Test ule selects.207define <8 x i16> @f19(<8 x i16> %val1, <8 x i16> %val2,208 <8 x i16> %val3, <8 x i16> %val4) {209; CHECK-LABEL: f19:210; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26211; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]212; CHECK-NEXT: br %r14213 %cmp = icmp ule <8 x i16> %val1, %val2214 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4215 ret <8 x i16> %ret216}217 218; Test ult selects.219define <8 x i16> @f20(<8 x i16> %val1, <8 x i16> %val2,220 <8 x i16> %val3, <8 x i16> %val4) {221; CHECK-LABEL: f20:222; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24223; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]224; CHECK-NEXT: br %r14225 %cmp = icmp ult <8 x i16> %val1, %val2226 %ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4227 ret <8 x i16> %ret228}229