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1; Test v4i32 comparisons.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test eq.6define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {7; CHECK-LABEL: f1:8; CHECK: vceqf %v24, %v26, %v289; CHECK-NEXT: br %r1410 %cmp = icmp eq <4 x i32> %val1, %val211 %ret = sext <4 x i1> %cmp to <4 x i32>12 ret <4 x i32> %ret13}14 15; Test ne.16define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {17; CHECK-LABEL: f2:18; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v2819; CHECK-NEXT: vno %v24, [[REG]], [[REG]]20; CHECK-NEXT: br %r1421 %cmp = icmp ne <4 x i32> %val1, %val222 %ret = sext <4 x i1> %cmp to <4 x i32>23 ret <4 x i32> %ret24}25 26; Test sgt.27define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {28; CHECK-LABEL: f3:29; CHECK: vchf %v24, %v26, %v2830; CHECK-NEXT: br %r1431 %cmp = icmp sgt <4 x i32> %val1, %val232 %ret = sext <4 x i1> %cmp to <4 x i32>33 ret <4 x i32> %ret34}35 36; Test sge.37define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {38; CHECK-LABEL: f4:39; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v2640; CHECK-NEXT: vno %v24, [[REG]], [[REG]]41; CHECK-NEXT: br %r1442 %cmp = icmp sge <4 x i32> %val1, %val243 %ret = sext <4 x i1> %cmp to <4 x i32>44 ret <4 x i32> %ret45}46 47; Test sle.48define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {49; CHECK-LABEL: f5:50; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v2851; CHECK-NEXT: vno %v24, [[REG]], [[REG]]52; CHECK-NEXT: br %r1453 %cmp = icmp sle <4 x i32> %val1, %val254 %ret = sext <4 x i1> %cmp to <4 x i32>55 ret <4 x i32> %ret56}57 58; Test slt.59define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {60; CHECK-LABEL: f6:61; CHECK: vchf %v24, %v28, %v2662; CHECK-NEXT: br %r1463 %cmp = icmp slt <4 x i32> %val1, %val264 %ret = sext <4 x i1> %cmp to <4 x i32>65 ret <4 x i32> %ret66}67 68; Test ugt.69define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {70; CHECK-LABEL: f7:71; CHECK: vchlf %v24, %v26, %v2872; CHECK-NEXT: br %r1473 %cmp = icmp ugt <4 x i32> %val1, %val274 %ret = sext <4 x i1> %cmp to <4 x i32>75 ret <4 x i32> %ret76}77 78; Test uge.79define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {80; CHECK-LABEL: f8:81; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v2682; CHECK-NEXT: vno %v24, [[REG]], [[REG]]83; CHECK-NEXT: br %r1484 %cmp = icmp uge <4 x i32> %val1, %val285 %ret = sext <4 x i1> %cmp to <4 x i32>86 ret <4 x i32> %ret87}88 89; Test ule.90define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {91; CHECK-LABEL: f9:92; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v2893; CHECK-NEXT: vno %v24, [[REG]], [[REG]]94; CHECK-NEXT: br %r1495 %cmp = icmp ule <4 x i32> %val1, %val296 %ret = sext <4 x i1> %cmp to <4 x i32>97 ret <4 x i32> %ret98}99 100; Test ult.101define <4 x i32> @f10(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {102; CHECK-LABEL: f10:103; CHECK: vchlf %v24, %v28, %v26104; CHECK-NEXT: br %r14105 %cmp = icmp ult <4 x i32> %val1, %val2106 %ret = sext <4 x i1> %cmp to <4 x i32>107 ret <4 x i32> %ret108}109 110; Test eq selects.111define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2,112 <4 x i32> %val3, <4 x i32> %val4) {113; CHECK-LABEL: f11:114; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26115; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]116; CHECK-NEXT: br %r14117 %cmp = icmp eq <4 x i32> %val1, %val2118 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4119 ret <4 x i32> %ret120}121 122; Test ne selects.123define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2,124 <4 x i32> %val3, <4 x i32> %val4) {125; CHECK-LABEL: f12:126; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26127; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]128; CHECK-NEXT: br %r14129 %cmp = icmp ne <4 x i32> %val1, %val2130 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4131 ret <4 x i32> %ret132}133 134; Test sgt selects.135define <4 x i32> @f13(<4 x i32> %val1, <4 x i32> %val2,136 <4 x i32> %val3, <4 x i32> %val4) {137; CHECK-LABEL: f13:138; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26139; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]140; CHECK-NEXT: br %r14141 %cmp = icmp sgt <4 x i32> %val1, %val2142 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4143 ret <4 x i32> %ret144}145 146; Test sge selects.147define <4 x i32> @f14(<4 x i32> %val1, <4 x i32> %val2,148 <4 x i32> %val3, <4 x i32> %val4) {149; CHECK-LABEL: f14:150; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24151; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]152; CHECK-NEXT: br %r14153 %cmp = icmp sge <4 x i32> %val1, %val2154 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4155 ret <4 x i32> %ret156}157 158; Test sle selects.159define <4 x i32> @f15(<4 x i32> %val1, <4 x i32> %val2,160 <4 x i32> %val3, <4 x i32> %val4) {161; CHECK-LABEL: f15:162; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26163; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]164; CHECK-NEXT: br %r14165 %cmp = icmp sle <4 x i32> %val1, %val2166 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4167 ret <4 x i32> %ret168}169 170; Test slt selects.171define <4 x i32> @f16(<4 x i32> %val1, <4 x i32> %val2,172 <4 x i32> %val3, <4 x i32> %val4) {173; CHECK-LABEL: f16:174; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24175; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]176; CHECK-NEXT: br %r14177 %cmp = icmp slt <4 x i32> %val1, %val2178 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4179 ret <4 x i32> %ret180}181 182; Test ugt selects.183define <4 x i32> @f17(<4 x i32> %val1, <4 x i32> %val2,184 <4 x i32> %val3, <4 x i32> %val4) {185; CHECK-LABEL: f17:186; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26187; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]188; CHECK-NEXT: br %r14189 %cmp = icmp ugt <4 x i32> %val1, %val2190 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4191 ret <4 x i32> %ret192}193 194; Test uge selects.195define <4 x i32> @f18(<4 x i32> %val1, <4 x i32> %val2,196 <4 x i32> %val3, <4 x i32> %val4) {197; CHECK-LABEL: f18:198; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24199; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]200; CHECK-NEXT: br %r14201 %cmp = icmp uge <4 x i32> %val1, %val2202 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4203 ret <4 x i32> %ret204}205 206; Test ule selects.207define <4 x i32> @f19(<4 x i32> %val1, <4 x i32> %val2,208 <4 x i32> %val3, <4 x i32> %val4) {209; CHECK-LABEL: f19:210; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26211; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]212; CHECK-NEXT: br %r14213 %cmp = icmp ule <4 x i32> %val1, %val2214 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4215 ret <4 x i32> %ret216}217 218; Test ult selects.219define <4 x i32> @f20(<4 x i32> %val1, <4 x i32> %val2,220 <4 x i32> %val3, <4 x i32> %val4) {221; CHECK-LABEL: f20:222; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24223; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]224; CHECK-NEXT: br %r14225 %cmp = icmp ult <4 x i32> %val1, %val2226 %ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4227 ret <4 x i32> %ret228}229