350 lines · plain
1; Test f32 and v4f32 comparisons on z14.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s4 5; Test oeq.6define <4 x i32> @f1(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {7; CHECK-LABEL: f1:8; CHECK: vfcesb %v24, %v26, %v289; CHECK-NEXT: br %r1410 %cmp = fcmp oeq <4 x float> %val1, %val211 %ret = sext <4 x i1> %cmp to <4 x i32>12 ret <4 x i32> %ret13}14 15; Test one.16define <4 x i32> @f2(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {17; CHECK-LABEL: f2:18; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v2619; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v26, %v2820; CHECK: vo %v24, [[REG1]], [[REG2]]21; CHECK-NEXT: br %r1422 %cmp = fcmp one <4 x float> %val1, %val223 %ret = sext <4 x i1> %cmp to <4 x i32>24 ret <4 x i32> %ret25}26 27; Test ogt.28define <4 x i32> @f3(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {29; CHECK-LABEL: f3:30; CHECK: vfchsb %v24, %v26, %v2831; CHECK-NEXT: br %r1432 %cmp = fcmp ogt <4 x float> %val1, %val233 %ret = sext <4 x i1> %cmp to <4 x i32>34 ret <4 x i32> %ret35}36 37; Test oge.38define <4 x i32> @f4(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {39; CHECK-LABEL: f4:40; CHECK: vfchesb %v24, %v26, %v2841; CHECK-NEXT: br %r1442 %cmp = fcmp oge <4 x float> %val1, %val243 %ret = sext <4 x i1> %cmp to <4 x i32>44 ret <4 x i32> %ret45}46 47; Test ole.48define <4 x i32> @f5(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {49; CHECK-LABEL: f5:50; CHECK: vfchesb %v24, %v28, %v2651; CHECK-NEXT: br %r1452 %cmp = fcmp ole <4 x float> %val1, %val253 %ret = sext <4 x i1> %cmp to <4 x i32>54 ret <4 x i32> %ret55}56 57; Test olt.58define <4 x i32> @f6(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {59; CHECK-LABEL: f6:60; CHECK: vfchsb %v24, %v28, %v2661; CHECK-NEXT: br %r1462 %cmp = fcmp olt <4 x float> %val1, %val263 %ret = sext <4 x i1> %cmp to <4 x i32>64 ret <4 x i32> %ret65}66 67; Test ueq.68define <4 x i32> @f7(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {69; CHECK-LABEL: f7:70; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v2671; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v26, %v2872; CHECK: vno %v24, [[REG1]], [[REG2]]73; CHECK-NEXT: br %r1474 %cmp = fcmp ueq <4 x float> %val1, %val275 %ret = sext <4 x i1> %cmp to <4 x i32>76 ret <4 x i32> %ret77}78 79; Test une.80define <4 x i32> @f8(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {81; CHECK-LABEL: f8:82; CHECK: vfcesb [[REG:%v[0-9]+]], %v26, %v2883; CHECK-NEXT: vno %v24, [[REG]], [[REG]]84; CHECK-NEXT: br %r1485 %cmp = fcmp une <4 x float> %val1, %val286 %ret = sext <4 x i1> %cmp to <4 x i32>87 ret <4 x i32> %ret88}89 90; Test ugt.91define <4 x i32> @f9(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {92; CHECK-LABEL: f9:93; CHECK: vfchesb [[REG:%v[0-9]+]], %v28, %v2694; CHECK-NEXT: vno %v24, [[REG]], [[REG]]95; CHECK-NEXT: br %r1496 %cmp = fcmp ugt <4 x float> %val1, %val297 %ret = sext <4 x i1> %cmp to <4 x i32>98 ret <4 x i32> %ret99}100 101; Test uge.102define <4 x i32> @f10(<4 x i32> %dummy, <4 x float> %val1,103 <4 x float> %val2) {104; CHECK-LABEL: f10:105; CHECK: vfchsb [[REG:%v[0-9]+]], %v28, %v26106; CHECK-NEXT: vno %v24, [[REG]], [[REG]]107; CHECK-NEXT: br %r14108 %cmp = fcmp uge <4 x float> %val1, %val2109 %ret = sext <4 x i1> %cmp to <4 x i32>110 ret <4 x i32> %ret111}112 113; Test ule.114define <4 x i32> @f11(<4 x i32> %dummy, <4 x float> %val1,115 <4 x float> %val2) {116; CHECK-LABEL: f11:117; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v28118; CHECK-NEXT: vno %v24, [[REG]], [[REG]]119; CHECK-NEXT: br %r14120 %cmp = fcmp ule <4 x float> %val1, %val2121 %ret = sext <4 x i1> %cmp to <4 x i32>122 ret <4 x i32> %ret123}124 125; Test ult.126define <4 x i32> @f12(<4 x i32> %dummy, <4 x float> %val1,127 <4 x float> %val2) {128; CHECK-LABEL: f12:129; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v28130; CHECK-NEXT: vno %v24, [[REG]], [[REG]]131; CHECK-NEXT: br %r14132 %cmp = fcmp ult <4 x float> %val1, %val2133 %ret = sext <4 x i1> %cmp to <4 x i32>134 ret <4 x i32> %ret135}136 137; Test ord.138define <4 x i32> @f13(<4 x i32> %dummy, <4 x float> %val1,139 <4 x float> %val2) {140; CHECK-LABEL: f13:141; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26142; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v26, %v28143; CHECK: vo %v24, [[REG1]], [[REG2]]144; CHECK-NEXT: br %r14145 %cmp = fcmp ord <4 x float> %val1, %val2146 %ret = sext <4 x i1> %cmp to <4 x i32>147 ret <4 x i32> %ret148}149 150; Test uno.151define <4 x i32> @f14(<4 x i32> %dummy, <4 x float> %val1,152 <4 x float> %val2) {153; CHECK-LABEL: f14:154; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26155; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v26, %v28156; CHECK: vno %v24, [[REG1]], [[REG2]]157; CHECK-NEXT: br %r14158 %cmp = fcmp uno <4 x float> %val1, %val2159 %ret = sext <4 x i1> %cmp to <4 x i32>160 ret <4 x i32> %ret161}162 163; Test oeq selects.164define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2,165 <4 x float> %val3, <4 x float> %val4) {166; CHECK-LABEL: f15:167; CHECK: vfcesb [[REG:%v[0-9]+]], %v24, %v26168; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]169; CHECK-NEXT: br %r14170 %cmp = fcmp oeq <4 x float> %val1, %val2171 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4172 ret <4 x float> %ret173}174 175; Test one selects.176define <4 x float> @f16(<4 x float> %val1, <4 x float> %val2,177 <4 x float> %val3, <4 x float> %val4) {178; CHECK-LABEL: f16:179; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24180; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v24, %v26181; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]182; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]183; CHECK-NEXT: br %r14184 %cmp = fcmp one <4 x float> %val1, %val2185 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4186 ret <4 x float> %ret187}188 189; Test ogt selects.190define <4 x float> @f17(<4 x float> %val1, <4 x float> %val2,191 <4 x float> %val3, <4 x float> %val4) {192; CHECK-LABEL: f17:193; CHECK: vfchsb [[REG:%v[0-9]+]], %v24, %v26194; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]195; CHECK-NEXT: br %r14196 %cmp = fcmp ogt <4 x float> %val1, %val2197 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4198 ret <4 x float> %ret199}200 201; Test oge selects.202define <4 x float> @f18(<4 x float> %val1, <4 x float> %val2,203 <4 x float> %val3, <4 x float> %val4) {204; CHECK-LABEL: f18:205; CHECK: vfchesb [[REG:%v[0-9]+]], %v24, %v26206; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]207; CHECK-NEXT: br %r14208 %cmp = fcmp oge <4 x float> %val1, %val2209 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4210 ret <4 x float> %ret211}212 213; Test ole selects.214define <4 x float> @f19(<4 x float> %val1, <4 x float> %val2,215 <4 x float> %val3, <4 x float> %val4) {216; CHECK-LABEL: f19:217; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v24218; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]219; CHECK-NEXT: br %r14220 %cmp = fcmp ole <4 x float> %val1, %val2221 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4222 ret <4 x float> %ret223}224 225; Test olt selects.226define <4 x float> @f20(<4 x float> %val1, <4 x float> %val2,227 <4 x float> %val3, <4 x float> %val4) {228; CHECK-LABEL: f20:229; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v24230; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]231; CHECK-NEXT: br %r14232 %cmp = fcmp olt <4 x float> %val1, %val2233 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4234 ret <4 x float> %ret235}236 237; Test ueq selects.238define <4 x float> @f21(<4 x float> %val1, <4 x float> %val2,239 <4 x float> %val3, <4 x float> %val4) {240; CHECK-LABEL: f21:241; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24242; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v24, %v26243; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]244; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]245; CHECK-NEXT: br %r14246 %cmp = fcmp ueq <4 x float> %val1, %val2247 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4248 ret <4 x float> %ret249}250 251; Test une selects.252define <4 x float> @f22(<4 x float> %val1, <4 x float> %val2,253 <4 x float> %val3, <4 x float> %val4) {254; CHECK-LABEL: f22:255; CHECK: vfcesb [[REG:%v[0-9]+]], %v24, %v26256; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]257; CHECK-NEXT: br %r14258 %cmp = fcmp une <4 x float> %val1, %val2259 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4260 ret <4 x float> %ret261}262 263; Test ugt selects.264define <4 x float> @f23(<4 x float> %val1, <4 x float> %val2,265 <4 x float> %val3, <4 x float> %val4) {266; CHECK-LABEL: f23:267; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v24268; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]269; CHECK-NEXT: br %r14270 %cmp = fcmp ugt <4 x float> %val1, %val2271 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4272 ret <4 x float> %ret273}274 275; Test uge selects.276define <4 x float> @f24(<4 x float> %val1, <4 x float> %val2,277 <4 x float> %val3, <4 x float> %val4) {278; CHECK-LABEL: f24:279; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v24280; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]281; CHECK-NEXT: br %r14282 %cmp = fcmp uge <4 x float> %val1, %val2283 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4284 ret <4 x float> %ret285}286 287; Test ule selects.288define <4 x float> @f25(<4 x float> %val1, <4 x float> %val2,289 <4 x float> %val3, <4 x float> %val4) {290; CHECK-LABEL: f25:291; CHECK: vfchsb [[REG:%v[0-9]+]], %v24, %v26292; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]293; CHECK-NEXT: br %r14294 %cmp = fcmp ule <4 x float> %val1, %val2295 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4296 ret <4 x float> %ret297}298 299; Test ult selects.300define <4 x float> @f26(<4 x float> %val1, <4 x float> %val2,301 <4 x float> %val3, <4 x float> %val4) {302; CHECK-LABEL: f26:303; CHECK: vfchesb [[REG:%v[0-9]+]], %v24, %v26304; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]305; CHECK-NEXT: br %r14306 %cmp = fcmp ult <4 x float> %val1, %val2307 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4308 ret <4 x float> %ret309}310 311; Test ord selects.312define <4 x float> @f27(<4 x float> %val1, <4 x float> %val2,313 <4 x float> %val3, <4 x float> %val4) {314; CHECK-LABEL: f27:315; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24316; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v24, %v26317; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]318; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]319; CHECK-NEXT: br %r14320 %cmp = fcmp ord <4 x float> %val1, %val2321 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4322 ret <4 x float> %ret323}324 325; Test uno selects.326define <4 x float> @f28(<4 x float> %val1, <4 x float> %val2,327 <4 x float> %val3, <4 x float> %val4) {328; CHECK-LABEL: f28:329; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24330; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v24, %v26331; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]332; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]333; CHECK-NEXT: br %r14334 %cmp = fcmp uno <4 x float> %val1, %val2335 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4336 ret <4 x float> %ret337}338 339; Test an f32 comparison that uses vector registers.340define i64 @f29(i64 %a, i64 %b, float %f1, <4 x float> %vec) {341; CHECK-LABEL: f29:342; CHECK: wfcsb %f0, %v24343; CHECK-NEXT: locgrne %r2, %r3344; CHECK: br %r14345 %f2 = extractelement <4 x float> %vec, i32 0346 %cond = fcmp oeq float %f1, %f2347 %res = select i1 %cond, i64 %a, i64 %b348 ret i64 %res349}350