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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test usage of VACC/VSCBI.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6define <16 x i8> @v16i8_subc_1(<16 x i8> %a, <16 x i8> %b) unnamed_addr {7; CHECK-LABEL: v16i8_subc_1:8; CHECK: # %bb.0:9; CHECK-NEXT: vscbib %v24, %v24, %v2610; CHECK-NEXT: br %r1411 %cmp = icmp uge <16 x i8> %a, %b12 %ext = zext <16 x i1> %cmp to <16 x i8>13 ret <16 x i8> %ext14}15 16define <16 x i8> @v16i8_subc_2(<16 x i8> %a, <16 x i8> %b) unnamed_addr {17; CHECK-LABEL: v16i8_subc_2:18; CHECK: # %bb.0:19; CHECK-NEXT: vscbib %v24, %v26, %v2420; CHECK-NEXT: br %r1421 %cmp = icmp ule <16 x i8> %a, %b22 %ext = zext <16 x i1> %cmp to <16 x i8>23 ret <16 x i8> %ext24}25 26define <16 x i8> @v16i8_addc_1(<16 x i8> %a, <16 x i8> %b) {27; CHECK-LABEL: v16i8_addc_1:28; CHECK: # %bb.0:29; CHECK-NEXT: vaccb %v24, %v24, %v2630; CHECK-NEXT: br %r1431 %sum = add <16 x i8> %a, %b32 %cmp = icmp ult <16 x i8> %sum, %a33 %ext = zext <16 x i1> %cmp to <16 x i8>34 ret <16 x i8> %ext35}36 37define <16 x i8> @v16i8_addc_2(<16 x i8> %a, <16 x i8> %b) {38; CHECK-LABEL: v16i8_addc_2:39; CHECK: # %bb.0:40; CHECK-NEXT: vaccb %v24, %v24, %v2641; CHECK-NEXT: br %r1442 %sum = add <16 x i8> %a, %b43 %cmp = icmp ult <16 x i8> %sum, %b44 %ext = zext <16 x i1> %cmp to <16 x i8>45 ret <16 x i8> %ext46}47 48define <16 x i8> @v16i8_addc_3(<16 x i8> %a, <16 x i8> %b) {49; CHECK-LABEL: v16i8_addc_3:50; CHECK: # %bb.0:51; CHECK-NEXT: vaccb %v24, %v24, %v2652; CHECK-NEXT: br %r1453 %sum = add <16 x i8> %a, %b54 %cmp = icmp ugt <16 x i8> %a, %sum55 %ext = zext <16 x i1> %cmp to <16 x i8>56 ret <16 x i8> %ext57}58 59define <16 x i8> @v16i8_addc_4(<16 x i8> %a, <16 x i8> %b) {60; CHECK-LABEL: v16i8_addc_4:61; CHECK: # %bb.0:62; CHECK-NEXT: vaccb %v24, %v24, %v2663; CHECK-NEXT: br %r1464 %sum = add <16 x i8> %a, %b65 %cmp = icmp ugt <16 x i8> %b, %sum66 %ext = zext <16 x i1> %cmp to <16 x i8>67 ret <16 x i8> %ext68}69 70define <8 x i16> @v8i16_subc_1(<8 x i16> %a, <8 x i16> %b) unnamed_addr {71; CHECK-LABEL: v8i16_subc_1:72; CHECK: # %bb.0:73; CHECK-NEXT: vscbih %v24, %v24, %v2674; CHECK-NEXT: br %r1475 %cmp = icmp uge <8 x i16> %a, %b76 %ext = zext <8 x i1> %cmp to <8 x i16>77 ret <8 x i16> %ext78}79 80define <8 x i16> @v8i16_subc_2(<8 x i16> %a, <8 x i16> %b) unnamed_addr {81; CHECK-LABEL: v8i16_subc_2:82; CHECK: # %bb.0:83; CHECK-NEXT: vscbih %v24, %v26, %v2484; CHECK-NEXT: br %r1485 %cmp = icmp ule <8 x i16> %a, %b86 %ext = zext <8 x i1> %cmp to <8 x i16>87 ret <8 x i16> %ext88}89 90define <8 x i16> @v8i16_addc_1(<8 x i16> %a, <8 x i16> %b) {91; CHECK-LABEL: v8i16_addc_1:92; CHECK: # %bb.0:93; CHECK-NEXT: vacch %v24, %v24, %v2694; CHECK-NEXT: br %r1495 %sum = add <8 x i16> %a, %b96 %cmp = icmp ult <8 x i16> %sum, %a97 %ext = zext <8 x i1> %cmp to <8 x i16>98 ret <8 x i16> %ext99}100 101define <8 x i16> @v8i16_addc_2(<8 x i16> %a, <8 x i16> %b) {102; CHECK-LABEL: v8i16_addc_2:103; CHECK: # %bb.0:104; CHECK-NEXT: vacch %v24, %v24, %v26105; CHECK-NEXT: br %r14106 %sum = add <8 x i16> %a, %b107 %cmp = icmp ult <8 x i16> %sum, %b108 %ext = zext <8 x i1> %cmp to <8 x i16>109 ret <8 x i16> %ext110}111 112define <8 x i16> @v8i16_addc_3(<8 x i16> %a, <8 x i16> %b) {113; CHECK-LABEL: v8i16_addc_3:114; CHECK: # %bb.0:115; CHECK-NEXT: vacch %v24, %v24, %v26116; CHECK-NEXT: br %r14117 %sum = add <8 x i16> %a, %b118 %cmp = icmp ugt <8 x i16> %a, %sum119 %ext = zext <8 x i1> %cmp to <8 x i16>120 ret <8 x i16> %ext121}122 123define <8 x i16> @v8i16_addc_4(<8 x i16> %a, <8 x i16> %b) {124; CHECK-LABEL: v8i16_addc_4:125; CHECK: # %bb.0:126; CHECK-NEXT: vacch %v24, %v24, %v26127; CHECK-NEXT: br %r14128 %sum = add <8 x i16> %a, %b129 %cmp = icmp ugt <8 x i16> %b, %sum130 %ext = zext <8 x i1> %cmp to <8 x i16>131 ret <8 x i16> %ext132}133 134define <4 x i32> @v4i32_subc_1(<4 x i32> %a, <4 x i32> %b) unnamed_addr {135; CHECK-LABEL: v4i32_subc_1:136; CHECK: # %bb.0:137; CHECK-NEXT: vscbif %v24, %v24, %v26138; CHECK-NEXT: br %r14139 %cmp = icmp uge <4 x i32> %a, %b140 %ext = zext <4 x i1> %cmp to <4 x i32>141 ret <4 x i32> %ext142}143 144define <4 x i32> @v4i32_subc_2(<4 x i32> %a, <4 x i32> %b) unnamed_addr {145; CHECK-LABEL: v4i32_subc_2:146; CHECK: # %bb.0:147; CHECK-NEXT: vscbif %v24, %v26, %v24148; CHECK-NEXT: br %r14149 %cmp = icmp ule <4 x i32> %a, %b150 %ext = zext <4 x i1> %cmp to <4 x i32>151 ret <4 x i32> %ext152}153 154define <4 x i32> @v4i32_addc_1(<4 x i32> %a, <4 x i32> %b) {155; CHECK-LABEL: v4i32_addc_1:156; CHECK: # %bb.0:157; CHECK-NEXT: vaccf %v24, %v24, %v26158; CHECK-NEXT: br %r14159 %sum = add <4 x i32> %a, %b160 %cmp = icmp ult <4 x i32> %sum, %a161 %ext = zext <4 x i1> %cmp to <4 x i32>162 ret <4 x i32> %ext163}164 165define <4 x i32> @v4i32_addc_2(<4 x i32> %a, <4 x i32> %b) {166; CHECK-LABEL: v4i32_addc_2:167; CHECK: # %bb.0:168; CHECK-NEXT: vaccf %v24, %v24, %v26169; CHECK-NEXT: br %r14170 %sum = add <4 x i32> %a, %b171 %cmp = icmp ult <4 x i32> %sum, %b172 %ext = zext <4 x i1> %cmp to <4 x i32>173 ret <4 x i32> %ext174}175 176define <4 x i32> @v4i32_addc_3(<4 x i32> %a, <4 x i32> %b) {177; CHECK-LABEL: v4i32_addc_3:178; CHECK: # %bb.0:179; CHECK-NEXT: vaccf %v24, %v24, %v26180; CHECK-NEXT: br %r14181 %sum = add <4 x i32> %a, %b182 %cmp = icmp ugt <4 x i32> %a, %sum183 %ext = zext <4 x i1> %cmp to <4 x i32>184 ret <4 x i32> %ext185}186 187define <4 x i32> @v4i32_addc_4(<4 x i32> %a, <4 x i32> %b) {188; CHECK-LABEL: v4i32_addc_4:189; CHECK: # %bb.0:190; CHECK-NEXT: vaccf %v24, %v24, %v26191; CHECK-NEXT: br %r14192 %sum = add <4 x i32> %a, %b193 %cmp = icmp ugt <4 x i32> %b, %sum194 %ext = zext <4 x i1> %cmp to <4 x i32>195 ret <4 x i32> %ext196}197 198define <2 x i64> @v2i64_subc_1(<2 x i64> %a, <2 x i64> %b) unnamed_addr {199; CHECK-LABEL: v2i64_subc_1:200; CHECK: # %bb.0:201; CHECK-NEXT: vscbig %v24, %v24, %v26202; CHECK-NEXT: br %r14203 %cmp = icmp uge <2 x i64> %a, %b204 %ext = zext <2 x i1> %cmp to <2 x i64>205 ret <2 x i64> %ext206}207 208define <2 x i64> @v2i64_subc_2(<2 x i64> %a, <2 x i64> %b) unnamed_addr {209; CHECK-LABEL: v2i64_subc_2:210; CHECK: # %bb.0:211; CHECK-NEXT: vscbig %v24, %v26, %v24212; CHECK-NEXT: br %r14213 %cmp = icmp ule <2 x i64> %a, %b214 %ext = zext <2 x i1> %cmp to <2 x i64>215 ret <2 x i64> %ext216}217 218define <2 x i64> @v2i64_addc_1(<2 x i64> %a, <2 x i64> %b) {219; CHECK-LABEL: v2i64_addc_1:220; CHECK: # %bb.0:221; CHECK-NEXT: vaccg %v24, %v24, %v26222; CHECK-NEXT: br %r14223 %sum = add <2 x i64> %a, %b224 %cmp = icmp ult <2 x i64> %sum, %a225 %ext = zext <2 x i1> %cmp to <2 x i64>226 ret <2 x i64> %ext227}228 229define <2 x i64> @v2i64_addc_2(<2 x i64> %a, <2 x i64> %b) {230; CHECK-LABEL: v2i64_addc_2:231; CHECK: # %bb.0:232; CHECK-NEXT: vaccg %v24, %v24, %v26233; CHECK-NEXT: br %r14234 %sum = add <2 x i64> %a, %b235 %cmp = icmp ult <2 x i64> %sum, %b236 %ext = zext <2 x i1> %cmp to <2 x i64>237 ret <2 x i64> %ext238}239 240define <2 x i64> @v2i64_addc_3(<2 x i64> %a, <2 x i64> %b) {241; CHECK-LABEL: v2i64_addc_3:242; CHECK: # %bb.0:243; CHECK-NEXT: vaccg %v24, %v24, %v26244; CHECK-NEXT: br %r14245 %sum = add <2 x i64> %a, %b246 %cmp = icmp ugt <2 x i64> %a, %sum247 %ext = zext <2 x i1> %cmp to <2 x i64>248 ret <2 x i64> %ext249}250 251define <2 x i64> @v2i64_addc_4(<2 x i64> %a, <2 x i64> %b) {252; CHECK-LABEL: v2i64_addc_4:253; CHECK: # %bb.0:254; CHECK-NEXT: vaccg %v24, %v24, %v26255; CHECK-NEXT: br %r14256 %sum = add <2 x i64> %a, %b257 %cmp = icmp ugt <2 x i64> %b, %sum258 %ext = zext <2 x i1> %cmp to <2 x i64>259 ret <2 x i64> %ext260}261