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1; Test that a vector select with a logic combination of two compares do not2; produce any unnecessary pack, unpack or shift instructions.3; And, Or and Xor are tested.4;5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s6; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CHECK-Z147 8define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {9; CHECK-LABEL: fun0:10; CHECK: # %bb.0:11; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v2612; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v28, %v3013; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]14; CHECK-NEXT: vsel %v24, %v25, %v27, %v015; CHECK-NEXT: br %r1416 %cmp0 = icmp eq <2 x i8> %val1, %val217 %cmp1 = icmp eq <2 x i8> %val3, %val418 %and = and <2 x i1> %cmp0, %cmp119 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val620 ret <2 x i8> %sel21}22 23define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {24; CHECK-LABEL: fun1:25; CHECK: # %bb.0:26; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v2627; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v28, %v3028; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]29; CHECK-NEXT: vuphb %v0, %v030; CHECK-NEXT: vsel %v24, %v25, %v27, %v031; CHECK-NEXT: br %r1432 %cmp0 = icmp eq <2 x i8> %val1, %val233 %cmp1 = icmp eq <2 x i8> %val3, %val434 %and = and <2 x i1> %cmp0, %cmp135 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val636 ret <2 x i16> %sel37}38 39define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {40; CHECK-LABEL: fun2:41; CHECK: # %bb.0:42; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v30, %v2743; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v2544; CHECK-DAG: vceqb [[REG2:%v[0-9]+]], %v24, %v2645; CHECK-DAG: vpkh [[REG3:%v[0-9]+]], [[REG1]], [[REG0]]46; CHECK-NEXT: vo %v0, [[REG2]], [[REG3]]47; CHECK-NEXT: vsel %v24, %v29, %v31, %v048; CHECK-NEXT: br %r1449 %cmp0 = icmp eq <16 x i8> %val1, %val250 %cmp1 = icmp eq <16 x i16> %val3, %val451 %and = or <16 x i1> %cmp0, %cmp152 %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val653 ret <16 x i8> %sel54}55 56define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {57; CHECK-LABEL: fun3:58; CHECK: # %bb.0:59; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v2660; CHECK-DAG: vuphb [[REG2:%v[0-9]+]], [[REG0]]61; CHECK-DAG: vuplb [[REG1:%v[0-9]+]], [[REG0]]62; CHECK-DAG: vceqh [[REG3:%v[0-9]+]], %v28, %v2563; CHECK-DAG: vceqh [[REG4:%v[0-9]+]], %v30, %v2764; CHECK-DAG: vl [[REG5:%v[0-9]+]], 176(%r15)65; CHECK-DAG: vl [[REG6:%v[0-9]+]], 160(%r15)66; CHECK-DAG: vo [[REG7:%v[0-9]+]], %v2, [[REG4]]67; CHECK-DAG: vo [[REG8:%v[0-9]+]], [[REG2]], [[REG3]]68; CHECK-DAG: vsel %v24, %v29, [[REG6]], [[REG8]]69; CHECK-DAG: vsel %v26, %v31, [[REG5]], [[REG7]]70; CHECK-NEXT: br %r1471 %cmp0 = icmp eq <16 x i8> %val1, %val272 %cmp1 = icmp eq <16 x i16> %val3, %val473 %and = or <16 x i1> %cmp0, %cmp174 %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val675 ret <16 x i16> %sel76}77 78define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {79; CHECK-LABEL: fun4:80; CHECK: # %bb.0:81; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v2882; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v26, %v3083; CHECK-DAG: vceqb [[REG2:%v[0-9]+]], %v25, %v2984; CHECK-DAG: vceqb [[REG3:%v[0-9]+]], %v27, %v3185; CHECK-DAG: vl [[REG4:%v[0-9]+]], 208(%r15)86; CHECK-DAG: vl [[REG5:%v[0-9]+]], 176(%r15)87; CHECK-DAG: vl [[REG6:%v[0-9]+]], 192(%r15)88; CHECK-DAG: vl [[REG7:%v[0-9]+]], 160(%r15)89; CHECK-DAG: vx [[REG8:%v[0-9]+]], [[REG1]], [[REG3]]90; CHECK-DAG: vx [[REG9:%v[0-9]+]], [[REG0]], [[REG2]]91; CHECK-DAG: vsel %v24, [[REG7]], [[REG6]], [[REG9]]92; CHECK-DAG: vsel %v26, [[REG5]], [[REG4]], [[REG8]]93; CHECK-NEXT: br %r1494 %cmp0 = icmp eq <32 x i8> %val1, %val295 %cmp1 = icmp eq <32 x i8> %val3, %val496 %and = xor <32 x i1> %cmp0, %cmp197 %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val698 ret <32 x i8> %sel99}100 101define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {102; CHECK-LABEL: fun5:103; CHECK: # %bb.0:104; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26105; CHECK-DAG: vpkh [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]106; CHECK-DAG: vceqb [[REG2:%v[0-9]+]], %v28, %v30107; CHECK-DAG: vo %v0, [[REG1]], [[REG2]]108; CHECK-DAG: vsel %v24, %v25, %v27, %v0109; CHECK-NEXT: br %r14110 %cmp0 = icmp eq <2 x i16> %val1, %val2111 %cmp1 = icmp eq <2 x i8> %val3, %val4112 %and = or <2 x i1> %cmp0, %cmp1113 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6114 ret <2 x i8> %sel115}116 117define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {118; CHECK-LABEL: fun6:119; CHECK: # %bb.0:120; CHECK-NEXT: vceqb %v1, %v28, %v30121; CHECK-NEXT: vceqh %v0, %v24, %v26122; CHECK-NEXT: vuphb %v1, %v1123; CHECK-NEXT: vo %v0, %v0, %v1124; CHECK-NEXT: vsel %v24, %v25, %v27, %v0125; CHECK-NEXT: br %r14126 %cmp0 = icmp eq <2 x i16> %val1, %val2127 %cmp1 = icmp eq <2 x i8> %val3, %val4128 %and = or <2 x i1> %cmp0, %cmp1129 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6130 ret <2 x i16> %sel131}132 133define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i32> %val5, <2 x i32> %val6) {134; CHECK-LABEL: fun7:135; CHECK: # %bb.0:136; CHECK-NEXT: vceqb %v1, %v28, %v30137; CHECK-NEXT: vceqh %v0, %v24, %v26138; CHECK-NEXT: vuphb %v1, %v1139; CHECK-NEXT: vo %v0, %v0, %v1140; CHECK-NEXT: vuphh %v0, %v0141; CHECK-NEXT: vsel %v24, %v25, %v27, %v0142; CHECK-NEXT: br %r14143 %cmp0 = icmp eq <2 x i16> %val1, %val2144 %cmp1 = icmp eq <2 x i8> %val3, %val4145 %and = or <2 x i1> %cmp0, %cmp1146 %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6147 ret <2 x i32> %sel148}149 150define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {151; CHECK-LABEL: fun8:152; CHECK: # %bb.0:153; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26154; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v30155; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]156; CHECK-NEXT: vpkh %v0, %v0, %v0157; CHECK-NEXT: vsel %v24, %v25, %v27, %v0158; CHECK-NEXT: br %r14159 %cmp0 = icmp eq <8 x i16> %val1, %val2160 %cmp1 = icmp eq <8 x i16> %val3, %val4161 %and = xor <8 x i1> %cmp0, %cmp1162 %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6163 ret <8 x i8> %sel164}165 166define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {167; CHECK-LABEL: fun9:168; CHECK: # %bb.0:169; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26170; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v30171; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]172; CHECK-NEXT: vsel %v24, %v25, %v27, %v0173; CHECK-NEXT: br %r14174 %cmp0 = icmp eq <8 x i16> %val1, %val2175 %cmp1 = icmp eq <8 x i16> %val3, %val4176 %and = xor <8 x i1> %cmp0, %cmp1177 %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6178 ret <8 x i16> %sel179}180 181define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {182; CHECK-LABEL: fun10:183; CHECK: # %bb.0:184; CHECK-DAG: vceqh [[REG0:%v[0-9]+]], %v24, %v26185; CHECK-DAG: vceqh [[REG1:%v[0-9]+]], %v28, %v30186; CHECK-NEXT: vx [[REG2:%v[0-9]+]], [[REG0]], [[REG1]]187; CHECK-DAG: vuphh [[REG3:%v[0-9]+]], [[REG2]]188; CHECK-DAG: vuplhw [[REG4:%v[0-9]+]], [[REG2]]189; CHECK-NEXT: vsel %v24, %v25, %v29, [[REG3]]190; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG4]]191; CHECK-NEXT: br %r14192 %cmp0 = icmp eq <8 x i16> %val1, %val2193 %cmp1 = icmp eq <8 x i16> %val3, %val4194 %and = xor <8 x i1> %cmp0, %cmp1195 %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6196 ret <8 x i32> %sel197}198 199define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {200; CHECK-LABEL: fun11:201; CHECK: # %bb.0:202; CHECK-DAG: vl [[REG0:%v[0-9]+]], 192(%r15)203; CHECK-DAG: vl [[REG1:%v[0-9]+]], 208(%r15)204; CHECK-DAG: vl [[REG2:%v[0-9]+]], 160(%r15)205; CHECK-DAG: vl [[REG3:%v[0-9]+]], 176(%r15)206; CHECK-DAG: vceqf [[REG4:%v[0-9]+]], %v27, [[REG3]]207; CHECK-DAG: vceqf [[REG5:%v[0-9]+]], %v25, [[REG2]]208; CHECK-DAG: vceqf [[REG6:%v[0-9]+]], %v31, [[REG1]]209; CHECK-DAG: vceqf [[REG7:%v[0-9]+]], %v29, [[REG0]]210; CHECK-DAG: vceqh [[REG8:%v[0-9]+]], %v24, %v28211; CHECK-DAG: vceqh [[REG9:%v[0-9]+]], %v26, %v30212; CHECK-DAG: vpkf [[REG10:%v[0-9]+]], [[REG5]], [[REG4]]213; CHECK-DAG: vpkf [[REG11:%v[0-9]+]], [[REG7]], [[REG6]]214; CHECK-DAG: vn [[REG12:%v[0-9]+]], [[REG9]], [[REG11]]215; CHECK-DAG: vn [[REG13:%v[0-9]+]], [[REG8]], [[REG10]]216; CHECK-DAG: vl [[REG14:%v[0-9]+]], 240(%r15)217; CHECK-DAG: vl [[REG15:%v[0-9]+]], 224(%r15)218; CHECK-DAG: vpkh [[REG16:%v[0-9]+]], [[REG13]], [[REG12]]219; CHECK-NEXT: vsel %v24, [[REG15]], [[REG14]], [[REG16]]220; CHECK-NEXT: br %r14221 %cmp0 = icmp eq <16 x i16> %val1, %val2222 %cmp1 = icmp eq <16 x i32> %val3, %val4223 %and = and <16 x i1> %cmp0, %cmp1224 %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6225 ret <16 x i8> %sel226}227 228define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i16> %val5, <16 x i16> %val6) {229; CHECK-LABEL: fun12:230; CHECK: # %bb.0:231; CHECK-DAG: vl [[REG0:%v[0-9]+]], 192(%r15)232; CHECK-DAG: vl [[REG1:%v[0-9]+]], 208(%r15)233; CHECK-DAG: vl [[REG2:%v[0-9]+]], 160(%r15)234; CHECK-DAG: vl [[REG3:%v[0-9]+]], 176(%r15)235; CHECK-DAG: vceqf [[REG4:%v[0-9]+]], %v27, [[REG3]]236; CHECK-DAG: vceqf [[REG5:%v[0-9]+]], %v25, [[REG2]]237; CHECK-DAG: vceqf [[REG6:%v[0-9]+]], %v31, [[REG1]]238; CHECK-DAG: vceqf [[REG7:%v[0-9]+]], %v29, [[REG0]]239; CHECK-DAG: vceqh [[REG8:%v[0-9]+]], %v24, %v28240; CHECK-DAG: vceqh [[REG9:%v[0-9]+]], %v26, %v30241; CHECK-DAG: vpkf [[REG10:%v[0-9]+]], [[REG5]], [[REG4]]242; CHECK-DAG: vpkf [[REG11:%v[0-9]+]], [[REG7]], [[REG6]]243; CHECK-DAG: vl [[REG12:%v[0-9]+]], 272(%r15)244; CHECK-DAG: vl [[REG13:%v[0-9]+]], 240(%r15)245; CHECK-DAG: vl [[REG14:%v[0-9]+]], 256(%r15)246; CHECK-DAG: vl [[REG15:%v[0-9]+]], 224(%r15)247; CHECK-DAG: vn [[REG16:%v[0-9]+]], [[REG9]], [[REG11]]248; CHECK-DAG: vn [[REG17:%v[0-9]+]], [[REG8]], [[REG10]]249; CHECK-DAG: vsel %v24, [[REG15]], [[REG14]], [[REG17]]250; CHECK-DAG: vsel %v26, [[REG13]], [[REG12]], [[REG16]]251; CHECK-NEXT: br %r14252 %cmp0 = icmp eq <16 x i16> %val1, %val2253 %cmp1 = icmp eq <16 x i32> %val3, %val4254 %and = and <16 x i1> %cmp0, %cmp1255 %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6256 ret <16 x i16> %sel257}258 259define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {260; CHECK-LABEL: fun13:261; CHECK: # %bb.0:262; CHECK-NEXT: vceqg %v1, %v28, %v30263; CHECK-NEXT: vceqf %v0, %v24, %v26264; CHECK-NEXT: vpkg %v1, %v1, %v1265; CHECK-NEXT: vx %v0, %v0, %v1266; CHECK-NEXT: vpkf %v0, %v0, %v0267; CHECK-NEXT: vsel %v24, %v25, %v27, %v0268; CHECK-NEXT: br %r14269 %cmp0 = icmp eq <2 x i32> %val1, %val2270 %cmp1 = icmp eq <2 x i64> %val3, %val4271 %and = xor <2 x i1> %cmp0, %cmp1272 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6273 ret <2 x i16> %sel274}275 276define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {277; CHECK-LABEL: fun14:278; CHECK: # %bb.0:279; CHECK-NEXT: vceqg %v1, %v28, %v30280; CHECK-NEXT: vceqf %v0, %v24, %v26281; CHECK-NEXT: vpkg %v1, %v1, %v1282; CHECK-NEXT: vx %v0, %v0, %v1283; CHECK-NEXT: vsel %v24, %v25, %v27, %v0284; CHECK-NEXT: br %r14285 %cmp0 = icmp eq <2 x i32> %val1, %val2286 %cmp1 = icmp eq <2 x i64> %val3, %val4287 %and = xor <2 x i1> %cmp0, %cmp1288 %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6289 ret <2 x i32> %sel290}291 292define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {293; CHECK-LABEL: fun15:294; CHECK: # %bb.0:295; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v26296; CHECK-DAG: vuphf [[REG1:%v[0-9]+]], [[REG0]]297; CHECK-DAG: vceqg [[REG2:%v[0-9]+]], %v28, %v30298; CHECK-NEXT: vx %v0, [[REG1]], [[REG2]]299; CHECK-NEXT: vsel %v24, %v25, %v27, %v0300; CHECK-NEXT: br %r14301 %cmp0 = icmp eq <2 x i32> %val1, %val2302 %cmp1 = icmp eq <2 x i64> %val3, %val4303 %and = xor <2 x i1> %cmp0, %cmp1304 %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6305 ret <2 x i64> %sel306}307 308define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i16> %val5, <4 x i16> %val6) {309; CHECK-LABEL: fun16:310; CHECK: # %bb.0:311; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v26312; CHECK-DAG: vpkf [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]313; CHECK-DAG: vceqh [[REG2:%v[0-9]+]], %v28, %v30314; CHECK-NEXT: vn %v0, [[REG1]], [[REG2]]315; CHECK-NEXT: vsel %v24, %v25, %v27, %v0316; CHECK-NEXT: br %r14317 %cmp0 = icmp eq <4 x i32> %val1, %val2318 %cmp1 = icmp eq <4 x i16> %val3, %val4319 %and = and <4 x i1> %cmp0, %cmp1320 %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6321 ret <4 x i16> %sel322}323 324define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i32> %val5, <4 x i32> %val6) {325; CHECK-LABEL: fun17:326; CHECK: # %bb.0:327; CHECK-NEXT: vceqh %v1, %v28, %v30328; CHECK-NEXT: vceqf %v0, %v24, %v26329; CHECK-NEXT: vuphh %v1, %v1330; CHECK-NEXT: vn %v0, %v0, %v1331; CHECK-NEXT: vsel %v24, %v25, %v27, %v0332; CHECK-NEXT: br %r14333 %cmp0 = icmp eq <4 x i32> %val1, %val2334 %cmp1 = icmp eq <4 x i16> %val3, %val4335 %and = and <4 x i1> %cmp0, %cmp1336 %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6337 ret <4 x i32> %sel338}339 340define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i64> %val5, <4 x i64> %val6) {341; CHECK-LABEL: fun18:342; CHECK: # %bb.0:343; CHECK-NEXT: vceqh %v1, %v28, %v30344; CHECK-NEXT: vceqf %v0, %v24, %v26345; CHECK-NEXT: vuphh %v1, %v1346; CHECK-NEXT: vn %v0, %v0, %v1347; CHECK-DAG: vuphf [[REG0:%v[0-9]+]], %v0348; CHECK-DAG: vuplf [[REG1:%v[0-9]+]], %v0349; CHECK-NEXT: vsel %v24, %v25, %v29, [[REG0]]350; CHECK-NEXT: vsel %v26, %v27, %v31, [[REG1]]351; CHECK-NEXT: br %r14352 %cmp0 = icmp eq <4 x i32> %val1, %val2353 %cmp1 = icmp eq <4 x i16> %val3, %val4354 %and = and <4 x i1> %cmp0, %cmp1355 %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6356 ret <4 x i64> %sel357}358 359define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i16> %val5, <8 x i16> %val6) {360; CHECK-LABEL: fun19:361; CHECK: # %bb.0:362; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v28363; CHECK-DAG: vceqf [[REG1:%v[0-9]+]], %v26, %v30364; CHECK-DAG: vceqf [[REG2:%v[0-9]+]], %v25, %v29365; CHECK-DAG: vceqf [[REG3:%v[0-9]+]], %v27, %v31366; CHECK-DAG: vo [[REG4:%v[0-9]+]], [[REG1]], [[REG3]]367; CHECK-DAG: vo [[REG5:%v[0-9]+]], [[REG0]], [[REG2]]368; CHECK-DAG: vl [[REG6:%v[0-9]+]], 176(%r15)369; CHECK-DAG: vl [[REG7:%v[0-9]+]], 160(%r15)370; CHECK-DAG: vpkf [[REG8:%v[0-9]+]], [[REG5]], [[REG4]]371; CHECK-NEXT: vsel %v24, [[REG7]], [[REG6]], [[REG8]]372; CHECK-NEXT: br %r14373 %cmp0 = icmp eq <8 x i32> %val1, %val2374 %cmp1 = icmp eq <8 x i32> %val3, %val4375 %and = or <8 x i1> %cmp0, %cmp1376 %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6377 ret <8 x i16> %sel378}379 380define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i32> %val5, <8 x i32> %val6) {381; CHECK-LABEL: fun20:382; CHECK: # %bb.0:383; CHECK-DAG: vceqf [[REG0:%v[0-9]+]], %v24, %v28384; CHECK-DAG: vceqf [[REG1:%v[0-9]+]], %v26, %v30385; CHECK-DAG: vceqf [[REG2:%v[0-9]+]], %v25, %v29386; CHECK-DAG: vceqf [[REG3:%v[0-9]+]], %v27, %v31387; CHECK-DAG: vl [[REG4:%v[0-9]+]], 208(%r15)388; CHECK-DAG: vl [[REG5:%v[0-9]+]], 176(%r15)389; CHECK-DAG: vl [[REG6:%v[0-9]+]], 192(%r15)390; CHECK-DAG: vl [[REG7:%v[0-9]+]], 160(%r15)391; CHECK-DAG: vo [[REG8:%v[0-9]+]], [[REG1]], [[REG3]]392; CHECK-DAG: vo [[REG9:%v[0-9]+]], [[REG0]], [[REG2]]393; CHECK-DAG: vsel %v24, [[REG7]], [[REG6]], [[REG9]]394; CHECK-DAG: vsel %v26, [[REG5]], [[REG4]], [[REG8]]395; CHECK-NEXT: br %r14396 %cmp0 = icmp eq <8 x i32> %val1, %val2397 %cmp1 = icmp eq <8 x i32> %val3, %val4398 %and = or <8 x i1> %cmp0, %cmp1399 %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6400 ret <8 x i32> %sel401}402 403define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {404; CHECK-LABEL: fun21:405; CHECK: # %bb.0:406; CHECK-DAG: vceqg [[REG0:%v[0-9]+]], %v24, %v26407; CHECK-DAG: vceqg [[REG1:%v[0-9]+]], %v28, %v30408; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]409; CHECK-NEXT: vpkg %v0, %v0, %v0410; CHECK-NEXT: vsel %v24, %v25, %v27, %v0411; CHECK-NEXT: br %r14412 %cmp0 = icmp eq <2 x i64> %val1, %val2413 %cmp1 = icmp eq <2 x i64> %val3, %val4414 %and = and <2 x i1> %cmp0, %cmp1415 %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6416 ret <2 x i32> %sel417}418 419define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {420; CHECK-LABEL: fun22:421; CHECK: # %bb.0:422; CHECK-DAG: vceqg [[REG0:%v[0-9]+]], %v24, %v26423; CHECK-DAG: vceqg [[REG1:%v[0-9]+]], %v28, %v30424; CHECK-NEXT: vn %v0, [[REG0]], [[REG1]]425; CHECK-NEXT: vsel %v24, %v25, %v27, %v0426; CHECK-NEXT: br %r14427 %cmp0 = icmp eq <2 x i64> %val1, %val2428 %cmp1 = icmp eq <2 x i64> %val3, %val4429 %and = and <2 x i1> %cmp0, %cmp1430 %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6431 ret <2 x i64> %sel432}433 434define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {435; CHECK-LABEL: fun23:436; CHECK: # %bb.0:437; CHECK-NEXT: vceqg %v0, %v26, %v30438; CHECK-NEXT: vceqg %v1, %v24, %v28439; CHECK-NEXT: vpkg %v0, %v1, %v0440; CHECK-NEXT: vceqf %v1, %v25, %v27441; CHECK-NEXT: vx %v0, %v0, %v1442; CHECK-NEXT: vsel %v24, %v29, %v31, %v0443; CHECK-NEXT: br %r14444 %cmp0 = icmp eq <4 x i64> %val1, %val2445 %cmp1 = icmp eq <4 x i32> %val3, %val4446 %and = xor <4 x i1> %cmp0, %cmp1447 %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6448 ret <4 x i32> %sel449}450 451define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {452; CHECK-LABEL: fun24:453; CHECK: # %bb.0:454; CHECK-NEXT: vceqf [[REG0:%v[0-9]+]], %v25, %v27455; CHECK-DAG: vuphf [[REG1:%v[0-9]+]], [[REG0]]456; CHECK-DAG: vuplf [[REG2:%v[0-9]+]], [[REG0]]457; CHECK-DAG: vceqg [[REG3:%v[0-9]+]], %v24, %v28458; CHECK-DAG: vceqg [[REG4:%v[0-9]+]], %v26, %v30459; CHECK-DAG: vl [[REG6:%v[0-9]+]], 176(%r15)460; CHECK-DAG: vl [[REG7:%v[0-9]+]], 160(%r15)461; CHECK-DAG: vx [[REG8:%v[0-9]+]], [[REG4]], [[REG2]]462; CHECK-DAG: vx [[REG9:%v[0-9]+]], [[REG3]], [[REG1]]463; CHECK-DAG: vsel %v24, %v29, [[REG7]], [[REG9]]464; CHECK-DAG: vsel %v26, %v31, [[REG6]], [[REG8]]465; CHECK-NEXT: br %r14466 %cmp0 = icmp eq <4 x i64> %val1, %val2467 %cmp1 = icmp eq <4 x i32> %val3, %val4468 %and = xor <4 x i1> %cmp0, %cmp1469 %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6470 ret <4 x i64> %sel471}472 473define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {474; CHECK-LABEL: fun25:475; CHECK: # %bb.0:476; CHECK-NEXT: vmrlf %v0, %v26, %v26477; CHECK-NEXT: vmrlf %v1, %v24, %v24478; CHECK-NEXT: vldeb %v0, %v0479; CHECK-NEXT: vldeb %v1, %v1480; CHECK-NEXT: vfchdb %v0, %v1, %v0481; CHECK-NEXT: vmrhf %v1, %v26, %v26482; CHECK-NEXT: vmrhf %v2, %v24, %v24483; CHECK-NEXT: vldeb %v1, %v1484; CHECK-NEXT: vldeb %v2, %v2485; CHECK-NEXT: vfchdb %v1, %v2, %v1486; CHECK-NEXT: vpkg %v0, %v1, %v0487; CHECK-NEXT: vfchdb %v1, %v28, %v30488; CHECK-NEXT: vpkg %v1, %v1, %v1489; CHECK-NEXT: vo %v0, %v0, %v1490; CHECK-NEXT: vsel %v24, %v25, %v27, %v0491; CHECK-NEXT: br %r14492;493; CHECK-Z14-LABEL: fun25:494; CHECK-Z14: # %bb.0:495; CHECK-Z14-NEXT: vfchdb %v1, %v28, %v30496; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26497; CHECK-Z14-NEXT: vpkg %v1, %v1, %v1498; CHECK-Z14-NEXT: vo %v0, %v0, %v1499; CHECK-Z14-NEXT: vsel %v24, %v25, %v27, %v0500; CHECK-Z14-NEXT: br %r14501 %cmp0 = fcmp ogt <2 x float> %val1, %val2502 %cmp1 = fcmp ogt <2 x double> %val3, %val4503 %and = or <2 x i1> %cmp0, %cmp1504 %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6505 ret <2 x float> %sel506}507 508define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {509; CHECK-LABEL: fun26:510; CHECK: # %bb.0:511; CHECK-NEXT: vmrlf %v0, %v26, %v26512; CHECK-NEXT: vmrlf %v1, %v24, %v24513; CHECK-NEXT: vldeb %v0, %v0514; CHECK-NEXT: vldeb %v1, %v1515; CHECK-NEXT: vfchdb %v0, %v1, %v0516; CHECK-NEXT: vmrhf %v1, %v26, %v26517; CHECK-NEXT: vmrhf %v2, %v24, %v24518; CHECK-NEXT: vldeb %v1, %v1519; CHECK-NEXT: vldeb %v2, %v2520; CHECK-NEXT: vfchdb %v1, %v2, %v1521; CHECK-NEXT: vpkg %v0, %v1, %v0522; CHECK-NEXT: vuphf %v0, %v0523; CHECK-NEXT: vfchdb %v1, %v28, %v30524; CHECK-NEXT: vo %v0, %v0, %v1525; CHECK-NEXT: vsel %v24, %v25, %v27, %v0526; CHECK-NEXT: br %r14527;528; CHECK-Z14-LABEL: fun26:529; CHECK-Z14: # %bb.0:530; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26531; CHECK-Z14-NEXT: vuphf %v0, %v0532; CHECK-Z14-NEXT: vfchdb %v1, %v28, %v30533; CHECK-Z14-NEXT: vo %v0, %v0, %v1534; CHECK-Z14-NEXT: vsel %v24, %v25, %v27, %v0535; CHECK-Z14-NEXT: br %r14536 %cmp0 = fcmp ogt <2 x float> %val1, %val2537 %cmp1 = fcmp ogt <2 x double> %val3, %val4538 %and = or <2 x i1> %cmp0, %cmp1539 %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6540 ret <2 x double> %sel541}542 543; Also check a widening select of a vector of floats544define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x float> %val5, <2 x float> %val6) {545; CHECK-LABEL: fun27:546; CHECK: # %bb.0:547; CHECK-DAG: vceqb [[REG0:%v[0-9]+]], %v24, %v26548; CHECK-DAG: vceqb [[REG1:%v[0-9]+]], %v28, %v30549; CHECK-NEXT: vo %v0, [[REG0]], [[REG1]]550; CHECK-NEXT: vuphb %v0, %v0551; CHECK-NEXT: vuphh %v0, %v0552; CHECK-NEXT: vsel %v24, %v25, %v27, %v0553; CHECK-NEXT: br %r14554 %cmp0 = icmp eq <2 x i8> %val1, %val2555 %cmp1 = icmp eq <2 x i8> %val3, %val4556 %and = or <2 x i1> %cmp0, %cmp1557 %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6558 ret <2 x float> %sel559}560 561define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {562; CHECK-LABEL: fun28:563; CHECK: # %bb.0:564; CHECK-DAG: vmrlf [[REG0:%v[0-9]+]], %v26, %v26565; CHECK-DAG: vmrlf [[REG1:%v[0-9]+]], %v24, %v24566; CHECK-DAG: vldeb [[REG2:%v[0-9]+]], [[REG0]]567; CHECK-DAG: vldeb [[REG3:%v[0-9]+]], [[REG1]]568; CHECK-DAG: vfchdb [[REG4:%v[0-9]+]], [[REG3]], [[REG2]]569; CHECK-DAG: vmrhf [[REG5:%v[0-9]+]], %v26, %v26570; CHECK-DAG: vmrhf [[REG6:%v[0-9]+]], %v24, %v24571; CHECK-DAG: vldeb [[REG7:%v[0-9]+]], [[REG5]]572; CHECK-DAG: vmrhf [[REG8:%v[0-9]+]], %v28, %v28573; CHECK-DAG: vldeb [[REG9:%v[0-9]+]], [[REG6]]574; CHECK-DAG: vfchdb [[REG10:%v[0-9]+]], [[REG9]], [[REG7]]575; CHECK-DAG: vpkg [[REG11:%v[0-9]+]], [[REG10]], [[REG4]]576; CHECK-DAG: vmrlf [[REG12:%v[0-9]+]], %v30, %v30577; CHECK-DAG: vmrlf [[REG13:%v[0-9]+]], %v28, %v28578; CHECK-DAG: vldeb [[REG14:%v[0-9]+]], [[REG12]]579; CHECK-DAG: vldeb [[REG15:%v[0-9]+]], [[REG13]]580; CHECK-DAG: vfchdb [[REG16:%v[0-9]+]], [[REG15]], [[REG14]]581; CHECK-DAG: vmrhf [[REG17:%v[0-9]+]], %v30, %v30582; CHECK-DAG: vldeb [[REG19:%v[0-9]+]], [[REG17]]583; CHECK-DAG: vldeb [[REG20:%v[0-9]+]], [[REG8]]584; CHECK-NEXT: vfchdb %v2, [[REG20]], [[REG19]]585; CHECK-NEXT: vpkg [[REG21:%v[0-9]+]], %v2, [[REG16]]586; CHECK-NEXT: vx %v0, [[REG11]], [[REG21]]587; CHECK-NEXT: vsel %v24, %v25, %v27, %v0588; CHECK-NEXT: br %r14589;590; CHECK-Z14-LABEL: fun28:591; CHECK-Z14: # %bb.0:592; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26593; CHECK-Z14-NEXT: vfchsb %v1, %v28, %v30594; CHECK-Z14-NEXT: vx %v0, %v0, %v1595; CHECK-Z14-NEXT: vsel %v24, %v25, %v27, %v0596; CHECK-Z14-NEXT: br %r14597 %cmp0 = fcmp ogt <4 x float> %val1, %val2598 %cmp1 = fcmp ogt <4 x float> %val3, %val4599 %and = xor <4 x i1> %cmp0, %cmp1600 %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6601 ret <4 x float> %sel602}603 604define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {605; CHECK-LABEL: fun29:606; CHECK: # %bb.0:607; CHECK-NEXT: vmrlf %v0, %v26, %v26608; CHECK-NEXT: vmrlf %v1, %v24, %v24609; CHECK-NEXT: vldeb %v0, %v0610; CHECK-NEXT: vldeb %v1, %v1611; CHECK-NEXT: vfchdb %v0, %v1, %v0612; CHECK-NEXT: vmrhf %v1, %v26, %v26613; CHECK-NEXT: vmrhf %v2, %v24, %v24614; CHECK-NEXT: vldeb %v1, %v1615; CHECK-NEXT: vmrhf %v3, %v28, %v28616; CHECK-NEXT: vldeb %v2, %v2617; CHECK-NEXT: vfchdb %v1, %v2, %v1618; CHECK-NEXT: vpkg %v0, %v1, %v0619; CHECK-NEXT: vmrlf %v1, %v30, %v30620; CHECK-NEXT: vmrlf %v2, %v28, %v28621; CHECK-NEXT: vldeb %v1, %v1622; CHECK-NEXT: vldeb %v2, %v2623; CHECK-NEXT: vfchdb %v1, %v2, %v1624; CHECK-NEXT: vmrhf %v2, %v30, %v30625; CHECK-NEXT: vldeb %v2, %v2626; CHECK-NEXT: vldeb %v3, %v3627; CHECK-NEXT: vfchdb %v2, %v3, %v2628; CHECK-NEXT: vpkg %v1, %v2, %v1629; CHECK-NEXT: vx %v0, %v0, %v1630; CHECK-NEXT: vuplf %v1, %v0631; CHECK-NEXT: vuphf %v0, %v0632; CHECK-NEXT: vsel %v24, %v25, %v29, %v0633; CHECK-NEXT: vsel %v26, %v27, %v31, %v1634; CHECK-NEXT: br %r14635;636; CHECK-Z14-LABEL: fun29:637; CHECK-Z14: # %bb.0:638; CHECK-Z14-NEXT: vfchsb %v0, %v24, %v26639; CHECK-Z14-NEXT: vfchsb %v1, %v28, %v30640; CHECK-Z14-NEXT: vx %v0, %v0, %v1641; CHECK-Z14-NEXT: vuplf %v1, %v0642; CHECK-Z14-NEXT: vuphf %v0, %v0643; CHECK-Z14-NEXT: vsel %v24, %v25, %v29, %v0644; CHECK-Z14-NEXT: vsel %v26, %v27, %v31, %v1645; CHECK-Z14-NEXT: br %r14646 %cmp0 = fcmp ogt <4 x float> %val1, %val2647 %cmp1 = fcmp ogt <4 x float> %val3, %val4648 %and = xor <4 x i1> %cmp0, %cmp1649 %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6650 ret <4 x double> %sel651}652 653define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x float> %val5, <8 x float> %val6) {654; CHECK-LABEL: fun30:655; CHECK: # %bb.0:656; CHECK-NEXT: vmrlf %v16, %v28, %v28657; CHECK-NEXT: vmrlf %v17, %v24, %v24658; CHECK-NEXT: vldeb %v16, %v16659; CHECK-NEXT: vldeb %v17, %v17660; CHECK-NEXT: vfchdb %v16, %v17, %v16661; CHECK-NEXT: vmrhf %v17, %v28, %v28662; CHECK-NEXT: vmrhf %v18, %v24, %v24663; CHECK-NEXT: vldeb %v17, %v17664; CHECK-NEXT: vl %v4, 192(%r15)665; CHECK-NEXT: vldeb %v18, %v18666; CHECK-NEXT: vl %v5, 208(%r15)667; CHECK-NEXT: vl %v6, 160(%r15)668; CHECK-NEXT: vl %v7, 176(%r15)669; CHECK-NEXT: vl %v0, 272(%r15)670; CHECK-NEXT: vl %v1, 240(%r15)671; CHECK-NEXT: vfchdb %v17, %v18, %v17672; CHECK-NEXT: vl %v2, 256(%r15)673; CHECK-NEXT: vl %v3, 224(%r15)674; CHECK-NEXT: vpkg %v16, %v17, %v16675; CHECK-NEXT: vmrlf %v17, %v30, %v30676; CHECK-NEXT: vmrlf %v18, %v26, %v26677; CHECK-NEXT: vmrhf %v19, %v26, %v26678; CHECK-NEXT: vfchdb %v7, %v27, %v7679; CHECK-NEXT: vfchdb %v6, %v25, %v6680; CHECK-NEXT: vfchdb %v5, %v31, %v5681; CHECK-NEXT: vfchdb %v4, %v29, %v4682; CHECK-NEXT: vpkg %v6, %v6, %v7683; CHECK-NEXT: vpkg %v4, %v4, %v5684; CHECK-NEXT: vn %v5, %v16, %v6685; CHECK-DAG: vsel %v24, %v3, %v2, %v5686; CHECK-DAG: vldeb %v17, %v17687; CHECK-NEXT: vldeb %v18, %v18688; CHECK-NEXT: vfchdb %v17, %v18, %v17689; CHECK-NEXT: vmrhf %v18, %v30, %v30690; CHECK-NEXT: vldeb %v18, %v18691; CHECK-NEXT: vldeb %v19, %v19692; CHECK-NEXT: vfchdb %v18, %v19, %v18693; CHECK-NEXT: vpkg %v17, %v18, %v17694; CHECK-NEXT: vn %v4, %v17, %v4695; CHECK-NEXT: vsel %v26, %v1, %v0, %v4696; CHECK-NEXT: br %r14697;698; CHECK-Z14-LABEL: fun30:699; CHECK-Z14: # %bb.0:700; CHECK-Z14-NEXT: vl %v4, 192(%r15)701; CHECK-Z14-NEXT: vl %v5, 208(%r15)702; CHECK-Z14-NEXT: vl %v6, 160(%r15)703; CHECK-Z14-NEXT: vl %v7, 176(%r15)704; CHECK-Z14-NEXT: vfchdb %v7, %v27, %v7705; CHECK-Z14-NEXT: vfchdb %v6, %v25, %v6706; CHECK-Z14-NEXT: vfchdb %v5, %v31, %v5707; CHECK-Z14-NEXT: vfchdb %v4, %v29, %v4708; CHECK-Z14-DAG: vfchsb %v16, %v24, %v28709; CHECK-Z14-DAG: vfchsb %v17, %v26, %v30710; CHECK-Z14-DAG: vpkg %v6, %v6, %v7711; CHECK-Z14-DAG: vpkg %v4, %v4, %v5712; CHECK-Z14-DAG: vl %v0, 272(%r15)713; CHECK-Z14-DAG: vl %v1, 240(%r15)714; CHECK-Z14-DAG: vl %v2, 256(%r15)715; CHECK-Z14-DAG: vl %v3, 224(%r15)716; CHECK-Z14-NEXT: vn %v4, %v17, %v4717; CHECK-Z14-NEXT: vn %v5, %v16, %v6718; CHECK-Z14-NEXT: vsel %v24, %v3, %v2, %v5719; CHECK-Z14-NEXT: vsel %v26, %v1, %v0, %v4720; CHECK-Z14-NEXT: br %r14721 %cmp0 = fcmp ogt <8 x float> %val1, %val2722 %cmp1 = fcmp ogt <8 x double> %val3, %val4723 %and = and <8 x i1> %cmp0, %cmp1724 %sel = select <8 x i1> %and, <8 x float> %val5, <8 x float> %val6725 ret <8 x float> %sel726}727 728define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {729; CHECK-LABEL: fun31:730; CHECK: # %bb.0:731; CHECK-DAG: vfchdb [[REG0:%v[0-9]+]], %v24, %v26732; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v30733; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]734; CHECK-NEXT: vpkg %v0, %v0, %v0735; CHECK-NEXT: vsel %v24, %v25, %v27, %v0736; CHECK-NEXT: br %r14737 %cmp0 = fcmp ogt <2 x double> %val1, %val2738 %cmp1 = fcmp ogt <2 x double> %val3, %val4739 %and = xor <2 x i1> %cmp0, %cmp1740 %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6741 ret <2 x float> %sel742}743 744define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {745; CHECK-LABEL: fun32:746; CHECK: # %bb.0:747; CHECK-DAG: vfchdb [[REG0:%v[0-9]+]], %v24, %v26748; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v30749; CHECK-NEXT: vx %v0, [[REG0]], [[REG1]]750; CHECK-NEXT: vsel %v24, %v25, %v27, %v0751; CHECK-NEXT: br %r14752 %cmp0 = fcmp ogt <2 x double> %val1, %val2753 %cmp1 = fcmp ogt <2 x double> %val3, %val4754 %and = xor <2 x i1> %cmp0, %cmp1755 %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6756 ret <2 x double> %sel757}758 759define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {760; CHECK-LABEL: fun33:761; CHECK: # %bb.0:762; CHECK-NEXT: vfchdb %v0, %v26, %v30763; CHECK-NEXT: vfchdb %v1, %v24, %v28764; CHECK-NEXT: vpkg %v0, %v1, %v0765; CHECK-NEXT: vmrlf %v1, %v27, %v27766; CHECK-NEXT: vmrlf %v2, %v25, %v25767; CHECK-NEXT: vldeb %v1, %v1768; CHECK-NEXT: vldeb %v2, %v2769; CHECK-NEXT: vfchdb %v1, %v2, %v1770; CHECK-NEXT: vmrhf %v2, %v27, %v27771; CHECK-NEXT: vmrhf %v3, %v25, %v25772; CHECK-NEXT: vldeb %v2, %v2773; CHECK-NEXT: vldeb %v3, %v3774; CHECK-NEXT: vfchdb %v2, %v3, %v2775; CHECK-NEXT: vpkg %v1, %v2, %v1776; CHECK-NEXT: vn %v0, %v0, %v1777; CHECK-NEXT: vsel %v24, %v29, %v31, %v0778; CHECK-NEXT: br %r14779;780; CHECK-Z14-LABEL: fun33:781; CHECK-Z14: # %bb.0:782; CHECK-Z14-NEXT: vfchdb %v0, %v26, %v30783; CHECK-Z14-NEXT: vfchdb %v1, %v24, %v28784; CHECK-Z14-NEXT: vpkg %v0, %v1, %v0785; CHECK-Z14-NEXT: vfchsb %v1, %v25, %v27786; CHECK-Z14-NEXT: vn %v0, %v0, %v1787; CHECK-Z14-NEXT: vsel %v24, %v29, %v31, %v0788; CHECK-Z14-NEXT: br %r14789 %cmp0 = fcmp ogt <4 x double> %val1, %val2790 %cmp1 = fcmp ogt <4 x float> %val3, %val4791 %and = and <4 x i1> %cmp0, %cmp1792 %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6793 ret <4 x float> %sel794}795 796define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {797; CHECK-LABEL: fun34:798; CHECK: # %bb.0:799; CHECK-NEXT: vmrlf [[REG0:%v[0-9]+]], %v27, %v27800; CHECK-NEXT: vmrlf [[REG1:%v[0-9]+]], %v25, %v25801; CHECK-NEXT: vldeb [[REG2:%v[0-9]+]], [[REG0]]802; CHECK-NEXT: vldeb [[REG3:%v[0-9]+]], [[REG1]]803; CHECK-NEXT: vfchdb [[REG4:%v[0-9]+]], [[REG3]], [[REG2]]804; CHECK-NEXT: vmrhf [[REG5:%v[0-9]+]], %v27, %v27805; CHECK-NEXT: vmrhf [[REG6:%v[0-9]+]], %v25, %v25806; CHECK-DAG: vldeb [[REG7:%v[0-9]+]], [[REG5]]807; CHECK-DAG: vl [[REG8:%v[0-9]+]], 176(%r15)808; CHECK-DAG: vldeb [[REG9:%v[0-9]+]], [[REG6]]809; CHECK-DAG: vl [[REG10:%v[0-9]+]], 160(%r15)810; CHECK-DAG: vfchdb [[REG11:%v[0-9]+]], [[REG9]], [[REG7]]811; CHECK-DAG: vpkg [[REG12:%v[0-9]+]], [[REG11]], [[REG4]]812; CHECK-DAG: vuphf [[REG13:%v[0-9]+]], [[REG12]]813; CHECK-DAG: vuplf [[REG14:%v[0-9]+]], [[REG12]]814; CHECK-DAG: vfchdb [[REG15:%v[0-9]+]], %v24, %v28815; CHECK-DAG: vfchdb [[REG16:%v[0-9]+]], %v26, %v30816; CHECK-NEXT: vn [[REG18:%v[0-9]+]], [[REG16]], [[REG14]]817; CHECK-NEXT: vn [[REG19:%v[0-9]+]], [[REG15]], [[REG13]]818; CHECK-NEXT: vsel %v24, %v29, [[REG10]], [[REG19]]819; CHECK-NEXT: vsel %v26, %v31, [[REG8]], [[REG18]]820; CHECK-NEXT: br %r14821;822; CHECK-Z14-LABEL: fun34:823; CHECK-Z14: # %bb.0:824; CHECK-Z14-NEXT: vfchsb %v4, %v25, %v27825; CHECK-Z14-NEXT: vl %v0, 176(%r15)826; CHECK-Z14-NEXT: vl %v1, 160(%r15)827; CHECK-Z14-NEXT: vfchdb %v2, %v24, %v28828; CHECK-Z14-NEXT: vfchdb %v3, %v26, %v30829; CHECK-Z14-NEXT: vuphf %v5, %v4830; CHECK-Z14-NEXT: vuplf %v4, %v4831; CHECK-Z14-NEXT: vn %v3, %v3, %v4832; CHECK-Z14-NEXT: vn %v2, %v2, %v5833; CHECK-Z14-NEXT: vsel %v24, %v29, %v1, %v2834; CHECK-Z14-NEXT: vsel %v26, %v31, %v0, %v3835; CHECK-Z14-NEXT: br %r14836 %cmp0 = fcmp ogt <4 x double> %val1, %val2837 %cmp1 = fcmp ogt <4 x float> %val3, %val4838 %and = and <4 x i1> %cmp0, %cmp1839 %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6840 ret <4 x double> %sel841}842