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1; Test various target-specific DAG combiner patterns.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Check that an extraction followed by a truncation is effectively treated6; as a bitcast.7define void @f1(<4 x i32> %v1, <4 x i32> %v2, ptr %ptr1, ptr %ptr2) {8; CHECK-LABEL: f1:9; CHECK: vaf [[REG:%v[0-9]+]], %v24, %v2610; CHECK-DAG: vsteb [[REG]], 0(%r2), 311; CHECK-DAG: vsteb [[REG]], 0(%r3), 1512; CHECK: br %r1413 %add = add <4 x i32> %v1, %v214 %elem1 = extractelement <4 x i32> %add, i32 015 %elem2 = extractelement <4 x i32> %add, i32 316 %trunc1 = trunc i32 %elem1 to i817 %trunc2 = trunc i32 %elem2 to i818 store i8 %trunc1, ptr %ptr119 store i8 %trunc2, ptr %ptr220 ret void21}22 23; Test a case where a pack-type shuffle can be eliminated.24define i16 @f2(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {25; CHECK-LABEL: f2:26; CHECK-NOT: vpk27; CHECK-DAG: vaf [[REG1:%v[0-9]+]], %v24, %v2628; CHECK-DAG: vaf [[REG2:%v[0-9]+]], %v26, %v2829; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG1]], 330; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG2]], 731; CHECK: br %r1432 %add1 = add <4 x i32> %v1, %v233 %add2 = add <4 x i32> %v2, %v334 %shuffle = shufflevector <4 x i32> %add1, <4 x i32> %add2,35 <4 x i32> <i32 1, i32 3, i32 5, i32 7>36 %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>37 %elem1 = extractelement <8 x i16> %bitcast, i32 138 %elem2 = extractelement <8 x i16> %bitcast, i32 739 %res = add i16 %elem1, %elem240 ret i16 %res41}42 43; ...and again in a case where there's also a splat and a bitcast.44define i16 @f3(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {45; CHECK-LABEL: f3:46; CHECK-NOT: vrepg47; CHECK-NOT: vpk48; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v2649; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 650; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 351; CHECK: br %r1452 %add = add <4 x i32> %v1, %v253 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,54 <2 x i32> <i32 0, i32 0>55 %splatcast = bitcast <2 x i64> %splat to <4 x i32>56 %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,57 <4 x i32> <i32 1, i32 3, i32 5, i32 7>58 %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>59 %elem1 = extractelement <8 x i16> %bitcast, i32 260 %elem2 = extractelement <8 x i16> %bitcast, i32 761 %res = add i16 %elem1, %elem262 ret i16 %res63}64 65; ...and again with a merge low instead of a pack.66define i16 @f4(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {67; CHECK-LABEL: f4:68; CHECK-NOT: vrepg69; CHECK-NOT: vmr70; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v2671; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 672; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 373; CHECK: br %r1474 %add = add <4 x i32> %v1, %v275 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,76 <2 x i32> <i32 0, i32 0>77 %splatcast = bitcast <2 x i64> %splat to <4 x i32>78 %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,79 <4 x i32> <i32 2, i32 6, i32 3, i32 7>80 %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>81 %elem1 = extractelement <8 x i16> %bitcast, i32 482 %elem2 = extractelement <8 x i16> %bitcast, i32 783 %res = add i16 %elem1, %elem284 ret i16 %res85}86 87; ...and again with a merge high.88define i16 @f5(<4 x i32> %v1, <4 x i32> %v2, <2 x i64> %v3) {89; CHECK-LABEL: f5:90; CHECK-NOT: vrepg91; CHECK-NOT: vmr92; CHECK-DAG: vaf [[REG:%v[0-9]+]], %v24, %v2693; CHECK-DAG: vlgvh {{%r[0-5]}}, [[REG]], 294; CHECK-DAG: vlgvh {{%r[0-5]}}, %v28, 395; CHECK: br %r1496 %add = add <4 x i32> %v1, %v297 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,98 <2 x i32> <i32 0, i32 0>99 %splatcast = bitcast <2 x i64> %splat to <4 x i32>100 %shuffle = shufflevector <4 x i32> %add, <4 x i32> %splatcast,101 <4 x i32> <i32 0, i32 4, i32 1, i32 5>102 %bitcast = bitcast <4 x i32> %shuffle to <8 x i16>103 %elem1 = extractelement <8 x i16> %bitcast, i32 4104 %elem2 = extractelement <8 x i16> %bitcast, i32 7105 %res = add i16 %elem1, %elem2106 ret i16 %res107}108 109; Test a case where an unpack high can be eliminated from the usual110; load-extend sequence.111define void @f6(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {112; CHECK-LABEL: f6:113; CHECK: vlrepg [[REG:%v[0-9]+]], 0(%r2)114; CHECK-NOT: vup115; CHECK-DAG: vsteb [[REG]], 0(%r3), 1116; CHECK-DAG: vsteb [[REG]], 0(%r4), 2117; CHECK-DAG: vsteb [[REG]], 0(%r5), 7118; CHECK: br %r14119 %vec = load <8 x i8>, ptr %ptr1120 %ext = sext <8 x i8> %vec to <8 x i16>121 %elem1 = extractelement <8 x i16> %ext, i32 1122 %elem2 = extractelement <8 x i16> %ext, i32 2123 %elem3 = extractelement <8 x i16> %ext, i32 7124 %trunc1 = trunc i16 %elem1 to i8125 %trunc2 = trunc i16 %elem2 to i8126 %trunc3 = trunc i16 %elem3 to i8127 store i8 %trunc1, ptr %ptr2128 store i8 %trunc2, ptr %ptr3129 store i8 %trunc3, ptr %ptr4130 ret void131}132 133; ...and again with a bitcast inbetween.134define void @f7(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {135; CHECK-LABEL: f7:136; CHECK: vlrepf [[REG:%v[0-9]+]], 0(%r2)137; CHECK-NOT: vup138; CHECK-DAG: vsteb [[REG]], 0(%r3), 0139; CHECK-DAG: vsteb [[REG]], 0(%r4), 1140; CHECK-DAG: vsteb [[REG]], 0(%r5), 3141; CHECK: br %r14142 %vec = load <4 x i8>, ptr %ptr1143 %ext = sext <4 x i8> %vec to <4 x i32>144 %bitcast = bitcast <4 x i32> %ext to <8 x i16>145 %elem1 = extractelement <8 x i16> %bitcast, i32 1146 %elem2 = extractelement <8 x i16> %bitcast, i32 3147 %elem3 = extractelement <8 x i16> %bitcast, i32 7148 %trunc1 = trunc i16 %elem1 to i8149 %trunc2 = trunc i16 %elem2 to i8150 %trunc3 = trunc i16 %elem3 to i8151 store i8 %trunc1, ptr %ptr2152 store i8 %trunc2, ptr %ptr3153 store i8 %trunc3, ptr %ptr4154 ret void155}156 157; Test that a truncating store with a non-simple VT can be handled.158define void @f8(ptr %src, ptr %dst) {159; CHECK-LABEL: f8:160 %1 = load <12 x i32>, ptr %src, align 64161 %2 = extractelement <12 x i32> %1, i64 11162 %3 = trunc i32 %2 to i16163 store i16 %3, ptr %dst, align 2164 ret void165}166