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1; Test vector division. There is no native integer support for this,2; so the integer cases are really a test of the operation legalization code.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; Test a v16i8 division.7define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {8; CHECK-LABEL: f1:9; CHECK: vlvgp [[REG:%v[0-9]+]],10; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 011; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 112; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 213; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 314; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 415; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 516; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 617; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 818; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 919; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1020; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1121; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1222; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1323; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1424; CHECK: br %r1425 %ret = sdiv <16 x i8> %val1, %val226 ret <16 x i8> %ret27}28 29; Test a v8i16 division.30define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {31; CHECK-LABEL: f2:32; CHECK: vlvgp [[REG:%v[0-9]+]],33; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 034; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 135; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 236; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 437; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 538; CHECK-DAG: vlvgh [[REG]], {{%r[0-9]+}}, 639; CHECK: br %r1440 %ret = sdiv <8 x i16> %val1, %val241 ret <8 x i16> %ret42}43 44; Test a v4i32 division.45define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {46; CHECK-LABEL: f3:47; CHECK: vlvgp [[REG:%v[0-9]+]],48; CHECK-DAG: vlvgf [[REG]], {{%r[0-9]+}}, 049; CHECK-DAG: vlvgf [[REG]], {{%r[0-9]+}}, 250; CHECK: br %r1451 %ret = sdiv <4 x i32> %val1, %val252 ret <4 x i32> %ret53}54 55; Test a v2i64 division.56define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {57; CHECK-LABEL: f4:58; CHECK: vlvgp %v24,59; CHECK: br %r1460 %ret = sdiv <2 x i64> %val1, %val261 ret <2 x i64> %ret62}63 64; Test a v2f64 division.65define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,66 <2 x double> %val2) {67; CHECK-LABEL: f5:68; CHECK: vfddb %v24, %v26, %v2869; CHECK: br %r1470 %ret = fdiv <2 x double> %val1, %val271 ret <2 x double> %ret72}73 74; Test an f64 division that uses vector registers.75define double @f6(<2 x double> %val1, <2 x double> %val2) {76; CHECK-LABEL: f6:77; CHECK: wfddb %f0, %v24, %v2678; CHECK: br %r1479 %scalar1 = extractelement <2 x double> %val1, i32 080 %scalar2 = extractelement <2 x double> %val2, i32 081 %ret = fdiv double %scalar1, %scalar282 ret double %ret83}84