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1; Test vector division on z14.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s4 5; Test a v4f32 division.6define <4 x float> @f1(<4 x float> %dummy, <4 x float> %val1,7 <4 x float> %val2) {8; CHECK-LABEL: f1:9; CHECK: vfdsb %v24, %v26, %v2810; CHECK: br %r1411 %ret = fdiv <4 x float> %val1, %val212 ret <4 x float> %ret13}14 15; Test an f32 division that uses vector registers.16define float @f2(<4 x float> %val1, <4 x float> %val2) {17; CHECK-LABEL: f2:18; CHECK: wfdsb %f0, %v24, %v2619; CHECK: br %r1420 %scalar1 = extractelement <4 x float> %val1, i32 021 %scalar2 = extractelement <4 x float> %val2, i32 022 %ret = fdiv float %scalar1, %scalar223 ret float %ret24}25