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1; Test vector stores.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test v16i8 stores.6define void @f1(<16 x i8> %val, ptr %ptr) {7; CHECK-LABEL: f1:8; CHECK: vst %v24, 0(%r2), 39; CHECK: br %r1410 store <16 x i8> %val, ptr %ptr11 ret void12}13 14; Test v8i16 stores.15define void @f2(<8 x i16> %val, ptr %ptr) {16; CHECK-LABEL: f2:17; CHECK: vst %v24, 0(%r2), 318; CHECK: br %r1419 store <8 x i16> %val, ptr %ptr20 ret void21}22 23; Test v4i32 stores.24define void @f3(<4 x i32> %val, ptr %ptr) {25; CHECK-LABEL: f3:26; CHECK: vst %v24, 0(%r2), 327; CHECK: br %r1428 store <4 x i32> %val, ptr %ptr29 ret void30}31 32; Test v2i64 stores.33define void @f4(<2 x i64> %val, ptr %ptr) {34; CHECK-LABEL: f4:35; CHECK: vst %v24, 0(%r2), 336; CHECK: br %r1437 store <2 x i64> %val, ptr %ptr38 ret void39}40 41; Test v4f32 stores.42define void @f5(<4 x float> %val, ptr %ptr) {43; CHECK-LABEL: f5:44; CHECK: vst %v24, 0(%r2), 345; CHECK: br %r1446 store <4 x float> %val, ptr %ptr47 ret void48}49 50; Test v2f64 stores.51define void @f6(<2 x double> %val, ptr %ptr) {52; CHECK-LABEL: f6:53; CHECK: vst %v24, 0(%r2), 354; CHECK: br %r1455 store <2 x double> %val, ptr %ptr56 ret void57}58 59; Test the highest aligned in-range offset.60define void @f7(<16 x i8> %val, ptr %base) {61; CHECK-LABEL: f7:62; CHECK: vst %v24, 4080(%r2), 363; CHECK: br %r1464 %ptr = getelementptr <16 x i8>, ptr %base, i64 25565 store <16 x i8> %val, ptr %ptr66 ret void67}68 69; Test the highest unaligned in-range offset.70define void @f8(<16 x i8> %val, ptr %base) {71; CHECK-LABEL: f8:72; CHECK: vst %v24, 4095(%r2)73; CHECK: br %r1474 %addr = getelementptr i8, ptr %base, i64 409575 store <16 x i8> %val, ptr %addr, align 176 ret void77}78 79; Test the next offset up, which requires separate address logic,80define void @f9(<16 x i8> %val, ptr %base) {81; CHECK-LABEL: f9:82; CHECK: aghi %r2, 409683; CHECK: vst %v24, 0(%r2), 384; CHECK: br %r1485 %ptr = getelementptr <16 x i8>, ptr %base, i64 25686 store <16 x i8> %val, ptr %ptr87 ret void88}89 90; Test negative offsets, which also require separate address logic,91define void @f10(<16 x i8> %val, ptr %base) {92; CHECK-LABEL: f10:93; CHECK: aghi %r2, -1694; CHECK: vst %v24, 0(%r2), 395; CHECK: br %r1496 %ptr = getelementptr <16 x i8>, ptr %base, i64 -197 store <16 x i8> %val, ptr %ptr98 ret void99}100 101; Check that indexes are allowed.102define void @f11(<16 x i8> %val, ptr %base, i64 %index) {103; CHECK-LABEL: f11:104; CHECK: vst %v24, 0(%r3,%r2)105; CHECK: br %r14106 %addr = getelementptr i8, ptr %base, i64 %index107 store <16 x i8> %val, ptr %addr, align 1108 ret void109}110 111; Test v2i8 stores.112define void @f12(<2 x i8> %val, ptr %ptr) {113; CHECK-LABEL: f12:114; CHECK: vsteh %v24, 0(%r2), 0115; CHECK: br %r14116 store <2 x i8> %val, ptr %ptr117 ret void118}119 120; Test v4i8 stores.121define void @f13(<4 x i8> %val, ptr %ptr) {122; CHECK-LABEL: f13:123; CHECK: vstef %v24, 0(%r2)124; CHECK: br %r14125 store <4 x i8> %val, ptr %ptr126 ret void127}128 129; Test v8i8 stores.130define void @f14(<8 x i8> %val, ptr %ptr) {131; CHECK-LABEL: f14:132; CHECK: vsteg %v24, 0(%r2)133; CHECK: br %r14134 store <8 x i8> %val, ptr %ptr135 ret void136}137 138; Test v2i16 stores.139define void @f15(<2 x i16> %val, ptr %ptr) {140; CHECK-LABEL: f15:141; CHECK: vstef %v24, 0(%r2), 0142; CHECK: br %r14143 store <2 x i16> %val, ptr %ptr144 ret void145}146 147; Test v4i16 stores.148define void @f16(<4 x i16> %val, ptr %ptr) {149; CHECK-LABEL: f16:150; CHECK: vsteg %v24, 0(%r2)151; CHECK: br %r14152 store <4 x i16> %val, ptr %ptr153 ret void154}155 156; Test v2i32 stores.157define void @f17(<2 x i32> %val, ptr %ptr) {158; CHECK-LABEL: f17:159; CHECK: vsteg %v24, 0(%r2), 0160; CHECK: br %r14161 store <2 x i32> %val, ptr %ptr162 ret void163}164 165; Test v2f32 stores.166define void @f18(<2 x float> %val, ptr %ptr) {167; CHECK-LABEL: f18:168; CHECK: vsteg %v24, 0(%r2), 0169; CHECK: br %r14170 store <2 x float> %val, ptr %ptr171 ret void172}173 174; Test quadword-aligned stores.175define void @f19(<16 x i8> %val, ptr %ptr) {176; CHECK-LABEL: f19:177; CHECK: vst %v24, 0(%r2), 4178; CHECK: br %r14179 store <16 x i8> %val, ptr %ptr, align 16180 ret void181}182 183; Test that the alignment hint for VST is emitted also when CFG optimizer184; replaces two VSTs with just one that then carries two memoperands.185define void @f20() {186; CHECK-LABEL: f20:187; CHECK: vst %v0, 0(%r1), 3188; CHECK-NOT: vst189entry:190 switch i32 undef, label %exit [191 i32 1, label %bb1192 i32 2, label %bb2193 ]194 195bb1:196 %C1 = call ptr @foo()197 %I1 = insertelement <2 x ptr> poison, ptr %C1, i64 0198 %S1 = shufflevector <2 x ptr> %I1, <2 x ptr> poison, <2 x i32> zeroinitializer199 store <2 x ptr> %S1, ptr undef, align 8200 br label %exit201 202bb2:203 %C2 = call ptr @foo()204 %I2 = insertelement <2 x ptr> poison, ptr %C2, i64 0205 %S2 = shufflevector <2 x ptr> %I2, <2 x ptr> poison, <2 x i32> zeroinitializer206 store <2 x ptr> %S2, ptr undef, align 8207 br label %exit208 209exit:210 ret void211}212 213declare ptr @foo()214