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1; Test vector insertion of register variables.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test v16i8 insertion into the first element.6define <16 x i8> @f1(<16 x i8> %val, i8 %element) {7; CHECK-LABEL: f1:8; CHECK: vlvgb %v24, %r2, 09; CHECK: br %r1410 %ret = insertelement <16 x i8> %val, i8 %element, i32 011 ret <16 x i8> %ret12}13 14; Test v16i8 insertion into the last element.15define <16 x i8> @f2(<16 x i8> %val, i8 %element) {16; CHECK-LABEL: f2:17; CHECK: vlvgb %v24, %r2, 1518; CHECK: br %r1419 %ret = insertelement <16 x i8> %val, i8 %element, i32 1520 ret <16 x i8> %ret21}22 23; Test v16i8 insertion into a variable element.24define <16 x i8> @f3(<16 x i8> %val, i8 %element, i32 %index) {25; CHECK-LABEL: f3:26; CHECK: vlvgb %v24, %r2, 0(%r3)27; CHECK: br %r1428 %ret = insertelement <16 x i8> %val, i8 %element, i32 %index29 ret <16 x i8> %ret30}31 32; Test v8i16 insertion into the first element.33define <8 x i16> @f4(<8 x i16> %val, i16 %element) {34; CHECK-LABEL: f4:35; CHECK: vlvgh %v24, %r2, 036; CHECK: br %r1437 %ret = insertelement <8 x i16> %val, i16 %element, i32 038 ret <8 x i16> %ret39}40 41; Test v8i16 insertion into the last element.42define <8 x i16> @f5(<8 x i16> %val, i16 %element) {43; CHECK-LABEL: f5:44; CHECK: vlvgh %v24, %r2, 745; CHECK: br %r1446 %ret = insertelement <8 x i16> %val, i16 %element, i32 747 ret <8 x i16> %ret48}49 50; Test v8i16 insertion into a variable element.51define <8 x i16> @f6(<8 x i16> %val, i16 %element, i32 %index) {52; CHECK-LABEL: f6:53; CHECK: vlvgh %v24, %r2, 0(%r3)54; CHECK: br %r1455 %ret = insertelement <8 x i16> %val, i16 %element, i32 %index56 ret <8 x i16> %ret57}58 59; Test v4i32 insertion into the first element.60define <4 x i32> @f7(<4 x i32> %val, i32 %element) {61; CHECK-LABEL: f7:62; CHECK: vlvgf %v24, %r2, 063; CHECK: br %r1464 %ret = insertelement <4 x i32> %val, i32 %element, i32 065 ret <4 x i32> %ret66}67 68; Test v4i32 insertion into the last element.69define <4 x i32> @f8(<4 x i32> %val, i32 %element) {70; CHECK-LABEL: f8:71; CHECK: vlvgf %v24, %r2, 372; CHECK: br %r1473 %ret = insertelement <4 x i32> %val, i32 %element, i32 374 ret <4 x i32> %ret75}76 77; Test v4i32 insertion into a variable element.78define <4 x i32> @f9(<4 x i32> %val, i32 %element, i32 %index) {79; CHECK-LABEL: f9:80; CHECK: vlvgf %v24, %r2, 0(%r3)81; CHECK: br %r1482 %ret = insertelement <4 x i32> %val, i32 %element, i32 %index83 ret <4 x i32> %ret84}85 86; Test v2i64 insertion into the first element.87define <2 x i64> @f10(<2 x i64> %val, i64 %element) {88; CHECK-LABEL: f10:89; CHECK: vlvgg %v24, %r2, 090; CHECK: br %r1491 %ret = insertelement <2 x i64> %val, i64 %element, i32 092 ret <2 x i64> %ret93}94 95; Test v2i64 insertion into the last element.96define <2 x i64> @f11(<2 x i64> %val, i64 %element) {97; CHECK-LABEL: f11:98; CHECK: vlvgg %v24, %r2, 199; CHECK: br %r14100 %ret = insertelement <2 x i64> %val, i64 %element, i32 1101 ret <2 x i64> %ret102}103 104; Test v2i64 insertion into a variable element.105define <2 x i64> @f12(<2 x i64> %val, i64 %element, i32 %index) {106; CHECK-LABEL: f12:107; CHECK: vlvgg %v24, %r2, 0(%r3)108; CHECK: br %r14109 %ret = insertelement <2 x i64> %val, i64 %element, i32 %index110 ret <2 x i64> %ret111}112 113; Test v4f32 insertion into the first element.114define <4 x float> @f13(<4 x float> %val, float %element) {115; CHECK-LABEL: f13:116; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0117; CHECK: vlvgf %v24, [[REG]], 0118; CHECK: br %r14119 %ret = insertelement <4 x float> %val, float %element, i32 0120 ret <4 x float> %ret121}122 123; Test v4f32 insertion into the last element.124define <4 x float> @f14(<4 x float> %val, float %element) {125; CHECK-LABEL: f14:126; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0127; CHECK: vlvgf %v24, [[REG]], 3128; CHECK: br %r14129 %ret = insertelement <4 x float> %val, float %element, i32 3130 ret <4 x float> %ret131}132 133; Test v4f32 insertion into a variable element.134define <4 x float> @f15(<4 x float> %val, float %element, i32 %index) {135; CHECK-LABEL: f15:136; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0137; CHECK: vlvgf %v24, [[REG]], 0(%r2)138; CHECK: br %r14139 %ret = insertelement <4 x float> %val, float %element, i32 %index140 ret <4 x float> %ret141}142 143; Test v2f64 insertion into the first element.144define <2 x double> @f16(<2 x double> %val, double %element) {145; CHECK-LABEL: f16:146; CHECK: vpdi %v24, %v0, %v24, 1147; CHECK: br %r14148 %ret = insertelement <2 x double> %val, double %element, i32 0149 ret <2 x double> %ret150}151 152; Test v2f64 insertion into the last element.153define <2 x double> @f17(<2 x double> %val, double %element) {154; CHECK-LABEL: f17:155; CHECK: vpdi %v24, %v24, %v0, 0156; CHECK: br %r14157 %ret = insertelement <2 x double> %val, double %element, i32 1158 ret <2 x double> %ret159}160 161; Test v2f64 insertion into a variable element.162define <2 x double> @f18(<2 x double> %val, double %element, i32 %index) {163; CHECK-LABEL: f18:164; CHECK: lgdr [[REG:%r[0-5]]], %f0165; CHECK: vlvgg %v24, [[REG]], 0(%r2)166; CHECK: br %r14167 %ret = insertelement <2 x double> %val, double %element, i32 %index168 ret <2 x double> %ret169}170 171; Test v16i8 insertion into a variable element plus one.172define <16 x i8> @f19(<16 x i8> %val, i8 %element, i32 %index) {173; CHECK-LABEL: f19:174; CHECK: vlvgb %v24, %r2, 1(%r3)175; CHECK: br %r14176 %add = add i32 %index, 1177 %ret = insertelement <16 x i8> %val, i8 %element, i32 %add178 ret <16 x i8> %ret179}180