106 lines · plain
1; Test vector sign-extending loads.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test a v16i1->v16i8 extension.6define <16 x i8> @f1(ptr %ptr) {7; No expected output, but must compile.8 %val = load <16 x i1>, ptr %ptr9 %ret = sext <16 x i1> %val to <16 x i8>10 ret <16 x i8> %ret11}12 13; Test a v8i1->v8i16 extension.14define <8 x i16> @f2(ptr %ptr) {15; No expected output, but must compile.16 %val = load <8 x i1>, ptr %ptr17 %ret = sext <8 x i1> %val to <8 x i16>18 ret <8 x i16> %ret19}20 21; Test a v8i8->v8i16 extension.22define <8 x i16> @f3(ptr %ptr) {23; CHECK-LABEL: f3:24; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)25; CHECK: vuphb %v24, [[REG1]]26; CHECK: br %r1427 %val = load <8 x i8>, ptr %ptr28 %ret = sext <8 x i8> %val to <8 x i16>29 ret <8 x i16> %ret30}31 32; Test a v4i1->v4i32 extension.33define <4 x i32> @f4(ptr %ptr) {34; No expected output, but must compile.35 %val = load <4 x i1>, ptr %ptr36 %ret = sext <4 x i1> %val to <4 x i32>37 ret <4 x i32> %ret38}39 40; Test a v4i8->v4i32 extension.41define <4 x i32> @f5(ptr %ptr) {42; CHECK-LABEL: f5:43; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)44; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]45; CHECK: vuphh %v24, [[REG2]]46; CHECK: br %r1447 %val = load <4 x i8>, ptr %ptr48 %ret = sext <4 x i8> %val to <4 x i32>49 ret <4 x i32> %ret50}51 52; Test a v4i16->v4i32 extension.53define <4 x i32> @f6(ptr %ptr) {54; CHECK-LABEL: f6:55; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)56; CHECK: vuphh %v24, [[REG1]]57; CHECK: br %r1458 %val = load <4 x i16>, ptr %ptr59 %ret = sext <4 x i16> %val to <4 x i32>60 ret <4 x i32> %ret61}62 63; Test a v2i1->v2i64 extension.64define <2 x i64> @f7(ptr %ptr) {65; No expected output, but must compile.66 %val = load <2 x i1>, ptr %ptr67 %ret = sext <2 x i1> %val to <2 x i64>68 ret <2 x i64> %ret69}70 71; Test a v2i8->v2i64 extension.72define <2 x i64> @f8(ptr %ptr) {73; CHECK-LABEL: f8:74; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)75; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]76; CHECK: vuphh [[REG3:%v[0-9]+]], [[REG2]]77; CHECK: vuphf %v24, [[REG3]]78; CHECK: br %r1479 %val = load <2 x i8>, ptr %ptr80 %ret = sext <2 x i8> %val to <2 x i64>81 ret <2 x i64> %ret82}83 84; Test a v2i16->v2i64 extension.85define <2 x i64> @f9(ptr %ptr) {86; CHECK-LABEL: f9:87; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)88; CHECK: vuphh [[REG2:%v[0-9]+]], [[REG1]]89; CHECK: vuphf %v24, [[REG2]]90; CHECK: br %r1491 %val = load <2 x i16>, ptr %ptr92 %ret = sext <2 x i16> %val to <2 x i64>93 ret <2 x i64> %ret94}95 96; Test a v2i32->v2i64 extension.97define <2 x i64> @f10(ptr %ptr) {98; CHECK-LABEL: f10:99; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)100; CHECK: vuphf %v24, [[REG1]]101; CHECK: br %r14102 %val = load <2 x i32>, ptr %ptr103 %ret = sext <2 x i32> %val to <2 x i64>104 ret <2 x i64> %ret105}106