108 lines · plain
1; Test vector zero-extending loads.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test a v16i1->v16i8 extension.6define <16 x i8> @f1(ptr %ptr) {7; No expected output, but must compile.8 %val = load <16 x i1>, ptr %ptr9 %ret = zext <16 x i1> %val to <16 x i8>10 ret <16 x i8> %ret11}12 13; Test a v8i1->v8i16 extension.14define <8 x i16> @f2(ptr %ptr) {15; No expected output, but must compile.16 %val = load <8 x i1>, ptr %ptr17 %ret = zext <8 x i1> %val to <8 x i16>18 ret <8 x i16> %ret19}20 21; Test a v8i8->v8i16 extension.22define <8 x i16> @f3(ptr %ptr) {23; CHECK-LABEL: f3:24; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)25; CHECK: vuplhb %v24, [[REG1]]26; CHECK: br %r1427 %val = load <8 x i8>, ptr %ptr28 %ret = zext <8 x i8> %val to <8 x i16>29 ret <8 x i16> %ret30}31 32; Test a v4i1->v4i32 extension.33define <4 x i32> @f4(ptr %ptr) {34; No expected output, but must compile.35 %val = load <4 x i1>, ptr %ptr36 %ret = zext <4 x i1> %val to <4 x i32>37 ret <4 x i32> %ret38}39 40; Test a v4i8->v4i32 extension.41define <4 x i32> @f5(ptr %ptr) {42; CHECK-LABEL: f5:43; CHECK: larl %r1, .LCPI4_044; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)45; CHECK: vl %v1, 0(%r1), 346; CHECK: vperm %v24, %v1, [[REG1]], %v147; CHECK: br %r1448 %val = load <4 x i8>, ptr %ptr49 %ret = zext <4 x i8> %val to <4 x i32>50 ret <4 x i32> %ret51}52 53; Test a v4i16->v4i32 extension.54define <4 x i32> @f6(ptr %ptr) {55; CHECK-LABEL: f6:56; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)57; CHECK: vuplhh %v24, [[REG1]]58; CHECK: br %r1459 %val = load <4 x i16>, ptr %ptr60 %ret = zext <4 x i16> %val to <4 x i32>61 ret <4 x i32> %ret62}63 64; Test a v2i1->v2i64 extension.65define <2 x i64> @f7(ptr %ptr) {66; No expected output, but must compile.67 %val = load <2 x i1>, ptr %ptr68 %ret = zext <2 x i1> %val to <2 x i64>69 ret <2 x i64> %ret70}71 72; Test a v2i8->v2i64 extension.73define <2 x i64> @f8(ptr %ptr) {74; CHECK-LABEL: f8:75; CHECK: larl %r1, .LCPI7_076; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)77; CHECK: vl %v1, 0(%r1), 378; CHECK: vperm %v24, %v1, [[REG1]], %v179; CHECK: br %r1480 %val = load <2 x i8>, ptr %ptr81 %ret = zext <2 x i8> %val to <2 x i64>82 ret <2 x i64> %ret83}84 85; Test a v2i16->v2i64 extension.86define <2 x i64> @f9(ptr %ptr) {87; CHECK-LABEL: f9:88; CHECK: larl %r1, .LCPI8_089; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)90; CHECK: vl %v1, 0(%r1), 391; CHECK: vperm %v24, %v1, [[REG1]], %v192; CHECK: br %r1493 %val = load <2 x i16>, ptr %ptr94 %ret = zext <2 x i16> %val to <2 x i64>95 ret <2 x i64> %ret96}97 98; Test a v2i32->v2i64 extension.99define <2 x i64> @f10(ptr %ptr) {100; CHECK-LABEL: f10:101; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)102; CHECK: vuplhf %v24, [[REG1]]103; CHECK: br %r14104 %val = load <2 x i32>, ptr %ptr105 %ret = zext <2 x i32> %val to <2 x i64>106 ret <2 x i64> %ret107}108