287 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test widening vector multiplication.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; Test a v16i8 -> v8i16 unsigned widening multiplication7; which is not folded into an even/odd widening operation.8define <8 x i16> @f1_not(<16 x i8> %val1, <16 x i8> %val2) {9; CHECK-LABEL: f1_not:10; CHECK: # %bb.0:11; CHECK-NEXT: vuplhb %v0, %v2412; CHECK-NEXT: vuplhb %v1, %v2613; CHECK-NEXT: vmlhw %v24, %v0, %v114; CHECK-NEXT: br %r1415 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>16 %zext1 = zext <8 x i8> %shuf1 to <8 x i16>17 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>18 %zext2 = zext <8 x i8> %shuf2 to <8 x i16>19 %ret = mul <8 x i16> %zext1, %zext220 ret <8 x i16> %ret21}22 23; Test a v16i8 (even) -> v8i16 unsigned widening multiplication.24define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2) {25; CHECK-LABEL: f1:26; CHECK: # %bb.0:27; CHECK-NEXT: vmleb %v24, %v24, %v2628; CHECK-NEXT: br %r1429 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>30 %zext1 = zext <8 x i8> %shuf1 to <8 x i16>31 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>32 %zext2 = zext <8 x i8> %shuf2 to <8 x i16>33 %ret = mul <8 x i16> %zext1, %zext234 ret <8 x i16> %ret35}36 37; Test a v16i8 (odd) -> v8i16 unsigned widening multiplication.38define <8 x i16> @f2(<16 x i8> %val1, <16 x i8> %val2) {39; CHECK-LABEL: f2:40; CHECK: # %bb.0:41; CHECK-NEXT: vmlob %v24, %v24, %v2642; CHECK-NEXT: br %r1443 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>44 %zext1 = zext <8 x i8> %shuf1 to <8 x i16>45 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>46 %zext2 = zext <8 x i8> %shuf2 to <8 x i16>47 %ret = mul <8 x i16> %zext1, %zext248 ret <8 x i16> %ret49}50 51; Test a v16i8 -> v8i16 signed widening multiplication52; which is not folded into an even/odd widening operation.53define <8 x i16> @f3_not(<16 x i8> %val1, <16 x i8> %val2) {54; CHECK-LABEL: f3_not:55; CHECK: # %bb.0:56; CHECK-NEXT: vuphb %v0, %v2657; CHECK-NEXT: vuphb %v1, %v2458; CHECK-NEXT: vmlhw %v24, %v1, %v059; CHECK-NEXT: br %r1460 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>61 %sext1 = sext <8 x i8> %shuf1 to <8 x i16>62 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>63 %sext2 = sext <8 x i8> %shuf2 to <8 x i16>64 %ret = mul <8 x i16> %sext1, %sext265 ret <8 x i16> %ret66}67 68; Test a v16i8 (even) -> v8i16 signed widening multiplication.69define <8 x i16> @f3(<16 x i8> %val1, <16 x i8> %val2) {70; CHECK-LABEL: f3:71; CHECK: # %bb.0:72; CHECK-NEXT: vmeb %v24, %v24, %v2673; CHECK-NEXT: br %r1474 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>75 %sext1 = sext <8 x i8> %shuf1 to <8 x i16>76 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>77 %sext2 = sext <8 x i8> %shuf2 to <8 x i16>78 %ret = mul <8 x i16> %sext1, %sext279 ret <8 x i16> %ret80}81 82; Test a v16i8 (odd) -> v8i16 signed widening multiplication.83define <8 x i16> @f4(<16 x i8> %val1, <16 x i8> %val2) {84; CHECK-LABEL: f4:85; CHECK: # %bb.0:86; CHECK-NEXT: vmob %v24, %v24, %v2687; CHECK-NEXT: br %r1488 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>89 %sext1 = sext <8 x i8> %shuf1 to <8 x i16>90 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>91 %sext2 = sext <8 x i8> %shuf2 to <8 x i16>92 %ret = mul <8 x i16> %sext1, %sext293 ret <8 x i16> %ret94}95 96; Test a v8i16 -> v4i32 unsigned widening multiplication97; which is not folded into an even/odd widening operation.98define <4 x i32> @f5_not(<8 x i16> %val1, <8 x i16> %val2) {99; CHECK-LABEL: f5_not:100; CHECK: # %bb.0:101; CHECK-NEXT: vuplhh %v0, %v24102; CHECK-NEXT: vuplhh %v1, %v26103; CHECK-NEXT: vmlf %v24, %v0, %v1104; CHECK-NEXT: br %r14105 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>106 %zext1 = zext <4 x i16> %shuf1 to <4 x i32>107 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>108 %zext2 = zext <4 x i16> %shuf2 to <4 x i32>109 %ret = mul <4 x i32> %zext1, %zext2110 ret <4 x i32> %ret111}112 113; Test a v8i16 (even) -> v4i32 unsigned widening multiplication.114define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2) {115; CHECK-LABEL: f5:116; CHECK: # %bb.0:117; CHECK-NEXT: vmleh %v24, %v24, %v26118; CHECK-NEXT: br %r14119 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>120 %zext1 = zext <4 x i16> %shuf1 to <4 x i32>121 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>122 %zext2 = zext <4 x i16> %shuf2 to <4 x i32>123 %ret = mul <4 x i32> %zext1, %zext2124 ret <4 x i32> %ret125}126 127; Test a v8i16 (odd) -> v4i32 unsigned widening multiplication.128define <4 x i32> @f6(<8 x i16> %val1, <8 x i16> %val2) {129; CHECK-LABEL: f6:130; CHECK: # %bb.0:131; CHECK-NEXT: vmloh %v24, %v24, %v26132; CHECK-NEXT: br %r14133 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>134 %zext1 = zext <4 x i16> %shuf1 to <4 x i32>135 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>136 %zext2 = zext <4 x i16> %shuf2 to <4 x i32>137 %ret = mul <4 x i32> %zext1, %zext2138 ret <4 x i32> %ret139}140 141; Test a v8i16 -> v4i32 signed widening multiplication142; which is not folded into an even/odd widening operation.143define <4 x i32> @f7_not(<8 x i16> %val1, <8 x i16> %val2) {144; CHECK-LABEL: f7_not:145; CHECK: # %bb.0:146; CHECK-NEXT: vuphh %v0, %v26147; CHECK-NEXT: vuphh %v1, %v24148; CHECK-NEXT: vmlf %v24, %v1, %v0149; CHECK-NEXT: br %r14150 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>151 %sext1 = sext <4 x i16> %shuf1 to <4 x i32>152 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>153 %sext2 = sext <4 x i16> %shuf2 to <4 x i32>154 %ret = mul <4 x i32> %sext1, %sext2155 ret <4 x i32> %ret156}157 158; Test a v8i16 (even) -> v4i32 signed widening multiplication.159define <4 x i32> @f7(<8 x i16> %val1, <8 x i16> %val2) {160; CHECK-LABEL: f7:161; CHECK: # %bb.0:162; CHECK-NEXT: vmeh %v24, %v24, %v26163; CHECK-NEXT: br %r14164 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>165 %sext1 = sext <4 x i16> %shuf1 to <4 x i32>166 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>167 %sext2 = sext <4 x i16> %shuf2 to <4 x i32>168 %ret = mul <4 x i32> %sext1, %sext2169 ret <4 x i32> %ret170}171 172; Test a v8i16 (odd) -> v4i32 signed widening multiplication.173define <4 x i32> @f8(<8 x i16> %val1, <8 x i16> %val2) {174; CHECK-LABEL: f8:175; CHECK: # %bb.0:176; CHECK-NEXT: vmoh %v24, %v24, %v26177; CHECK-NEXT: br %r14178 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>179 %sext1 = sext <4 x i16> %shuf1 to <4 x i32>180 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>181 %sext2 = sext <4 x i16> %shuf2 to <4 x i32>182 %ret = mul <4 x i32> %sext1, %sext2183 ret <4 x i32> %ret184}185 186; Test a v4i32 -> v2i64 unsigned widening multiplication187; which is not folded into an even/odd widening operation.188define <2 x i64> @f9_not(<4 x i32> %val1, <4 x i32> %val2) {189; CHECK-LABEL: f9_not:190; CHECK: # %bb.0:191; CHECK-NEXT: vuplhf %v0, %v24192; CHECK-NEXT: vuplhf %v1, %v26193; CHECK-NEXT: vlgvg %r0, %v1, 1194; CHECK-NEXT: vlgvg %r1, %v0, 1195; CHECK-NEXT: msgr %r1, %r0196; CHECK-NEXT: vlgvg %r0, %v1, 0197; CHECK-NEXT: vlgvg %r2, %v0, 0198; CHECK-NEXT: msgr %r2, %r0199; CHECK-NEXT: vlvgp %v24, %r2, %r1200; CHECK-NEXT: br %r14201 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 1>202 %zext1 = zext <2 x i32> %shuf1 to <2 x i64>203 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 0, i32 1>204 %zext2 = zext <2 x i32> %shuf2 to <2 x i64>205 %ret = mul <2 x i64> %zext1, %zext2206 ret <2 x i64> %ret207}208 209; Test a v4i32 (even) -> v2i64 unsigned widening multiplication.210define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2) {211; CHECK-LABEL: f9:212; CHECK: # %bb.0:213; CHECK-NEXT: vmlef %v24, %v24, %v26214; CHECK-NEXT: br %r14215 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>216 %zext1 = zext <2 x i32> %shuf1 to <2 x i64>217 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 0, i32 2>218 %zext2 = zext <2 x i32> %shuf2 to <2 x i64>219 %ret = mul <2 x i64> %zext1, %zext2220 ret <2 x i64> %ret221}222 223; Test a v4i32 (odd) -> v2i64 unsigned widening multiplication.224define <2 x i64> @f10(<4 x i32> %val1, <4 x i32> %val2) {225; CHECK-LABEL: f10:226; CHECK: # %bb.0:227; CHECK-NEXT: vmlof %v24, %v24, %v26228; CHECK-NEXT: br %r14229 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>230 %zext1 = zext <2 x i32> %shuf1 to <2 x i64>231 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 1, i32 3>232 %zext2 = zext <2 x i32> %shuf2 to <2 x i64>233 %ret = mul <2 x i64> %zext1, %zext2234 ret <2 x i64> %ret235}236 237; Test a v4i32 -> v2i64 signed widening multiplication238; which is not folded into an even/odd widening operation.239define <2 x i64> @f11_not(<4 x i32> %val1, <4 x i32> %val2) {240; CHECK-LABEL: f11_not:241; CHECK: # %bb.0:242; CHECK-NEXT: vuphf %v0, %v24243; CHECK-NEXT: vuphf %v1, %v26244; CHECK-NEXT: vlgvg %r0, %v1, 1245; CHECK-NEXT: vlgvg %r1, %v0, 1246; CHECK-NEXT: msgr %r1, %r0247; CHECK-NEXT: vlgvg %r0, %v1, 0248; CHECK-NEXT: vlgvg %r2, %v0, 0249; CHECK-NEXT: msgr %r2, %r0250; CHECK-NEXT: vlvgp %v24, %r2, %r1251; CHECK-NEXT: br %r14252 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 1>253 %sext1 = sext <2 x i32> %shuf1 to <2 x i64>254 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 0, i32 1>255 %sext2 = sext <2 x i32> %shuf2 to <2 x i64>256 %ret = mul <2 x i64> %sext1, %sext2257 ret <2 x i64> %ret258}259 260; Test a v4i32 (even) -> v2i64 signed widening multiplication.261define <2 x i64> @f11(<4 x i32> %val1, <4 x i32> %val2) {262; CHECK-LABEL: f11:263; CHECK: # %bb.0:264; CHECK-NEXT: vmef %v24, %v24, %v26265; CHECK-NEXT: br %r14266 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>267 %sext1 = sext <2 x i32> %shuf1 to <2 x i64>268 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 0, i32 2>269 %sext2 = sext <2 x i32> %shuf2 to <2 x i64>270 %ret = mul <2 x i64> %sext1, %sext2271 ret <2 x i64> %ret272}273 274; Test a v4i32 (odd) -> v2i64 signed widening multiplication.275define <2 x i64> @f12(<4 x i32> %val1, <4 x i32> %val2) {276; CHECK-LABEL: f12:277; CHECK: # %bb.0:278; CHECK-NEXT: vmof %v24, %v24, %v26279; CHECK-NEXT: br %r14280 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>281 %sext1 = sext <2 x i32> %shuf1 to <2 x i64>282 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 1, i32 3>283 %sext2 = sext <2 x i32> %shuf2 to <2 x i64>284 %ret = mul <2 x i64> %sext1, %sext2285 ret <2 x i64> %ret286}287