65 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test widening vector multiplication on z17.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s5 6; Test a v2i64 (even) -> i128 unsigned widening multiplication.7define i128 @f1(<2 x i64> %val1, <2 x i64> %val2) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vmleg %v0, %v24, %v2611; CHECK-NEXT: vst %v0, 0(%r2), 312; CHECK-NEXT: br %r1413 %elt1 = extractelement <2 x i64> %val1, i32 014 %zext1 = zext i64 %elt1 to i12815 %elt2 = extractelement <2 x i64> %val2, i32 016 %zext2 = zext i64 %elt2 to i12817 %ret = mul i128 %zext1, %zext218 ret i128 %ret19}20 21; Test a v2i64 (odd) -> i128 unsigned widening multiplication.22define i128 @f2(<2 x i64> %val1, <2 x i64> %val2) {23; CHECK-LABEL: f2:24; CHECK: # %bb.0:25; CHECK-NEXT: vmlog %v0, %v24, %v2626; CHECK-NEXT: vst %v0, 0(%r2), 327; CHECK-NEXT: br %r1428 %elt1 = extractelement <2 x i64> %val1, i32 129 %zext1 = zext i64 %elt1 to i12830 %elt2 = extractelement <2 x i64> %val2, i32 131 %zext2 = zext i64 %elt2 to i12832 %ret = mul i128 %zext1, %zext233 ret i128 %ret34}35 36; Test a v2i64 (even) -> i128 signed widening multiplication.37define i128 @f3(<2 x i64> %val1, <2 x i64> %val2) {38; CHECK-LABEL: f3:39; CHECK: # %bb.0:40; CHECK-NEXT: vmeg %v0, %v24, %v2641; CHECK-NEXT: vst %v0, 0(%r2), 342; CHECK-NEXT: br %r1443 %elt1 = extractelement <2 x i64> %val1, i32 044 %sext1 = sext i64 %elt1 to i12845 %elt2 = extractelement <2 x i64> %val2, i32 046 %sext2 = sext i64 %elt2 to i12847 %ret = mul i128 %sext1, %sext248 ret i128 %ret49}50 51; Test a v2i64 (odd) -> i128 signed widening multiplication.52define i128 @f4(<2 x i64> %val1, <2 x i64> %val2) {53; CHECK-LABEL: f4:54; CHECK: # %bb.0:55; CHECK-NEXT: vmog %v0, %v24, %v2656; CHECK-NEXT: vst %v0, 0(%r2), 357; CHECK-NEXT: br %r1458 %elt1 = extractelement <2 x i64> %val1, i32 159 %sext1 = sext i64 %elt1 to i12860 %elt2 = extractelement <2 x i64> %val2, i32 161 %sext2 = sext i64 %elt2 to i12862 %ret = mul i128 %sext1, %sext263 ret i128 %ret64}65