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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test widening vector multiply-and-add.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; Test a v16i8 (even) -> v8i16 unsigned widening multiply-and-add.7define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vmaleb %v24, %v24, %v26, %v2811; CHECK-NEXT: br %r1412 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>13 %zext1 = zext <8 x i8> %shuf1 to <8 x i16>14 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>15 %zext2 = zext <8 x i8> %shuf2 to <8 x i16>16 %mul = mul <8 x i16> %zext1, %zext217 %ret = add <8 x i16> %mul, %val318 ret <8 x i16> %ret19}20 21; Test a v16i8 (odd) -> v8i16 unsigned widening multiply-and-add.22define <8 x i16> @f2(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {23; CHECK-LABEL: f2:24; CHECK: # %bb.0:25; CHECK-NEXT: vmalob %v24, %v24, %v26, %v2826; CHECK-NEXT: br %r1427 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>28 %zext1 = zext <8 x i8> %shuf1 to <8 x i16>29 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>30 %zext2 = zext <8 x i8> %shuf2 to <8 x i16>31 %mul = mul <8 x i16> %zext1, %zext232 %ret = add <8 x i16> %mul, %val333 ret <8 x i16> %ret34}35 36; Test a v16i8 (even) -> v8i16 signed widening multiply-and-add.37define <8 x i16> @f3(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {38; CHECK-LABEL: f3:39; CHECK: # %bb.0:40; CHECK-NEXT: vmaeb %v24, %v24, %v26, %v2841; CHECK-NEXT: br %r1442 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>43 %sext1 = sext <8 x i8> %shuf1 to <8 x i16>44 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>45 %sext2 = sext <8 x i8> %shuf2 to <8 x i16>46 %mul = mul <8 x i16> %sext1, %sext247 %ret = add <8 x i16> %mul, %val348 ret <8 x i16> %ret49}50 51; Test a v16i8 (odd) -> v8i16 signed widening multiply-and-add.52define <8 x i16> @f4(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {53; CHECK-LABEL: f4:54; CHECK: # %bb.0:55; CHECK-NEXT: vmaob %v24, %v24, %v26, %v2856; CHECK-NEXT: br %r1457 %shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>58 %sext1 = sext <8 x i8> %shuf1 to <8 x i16>59 %shuf2 = shufflevector <16 x i8> %val2, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>60 %sext2 = sext <8 x i8> %shuf2 to <8 x i16>61 %mul = mul <8 x i16> %sext1, %sext262 %ret = add <8 x i16> %mul, %val363 ret <8 x i16> %ret64}65 66; Test a v8i16 (even) -> v4i32 unsigned widening multiply-and-add.67define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {68; CHECK-LABEL: f5:69; CHECK: # %bb.0:70; CHECK-NEXT: vmaleh %v24, %v24, %v26, %v2871; CHECK-NEXT: br %r1472 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>73 %zext1 = zext <4 x i16> %shuf1 to <4 x i32>74 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>75 %zext2 = zext <4 x i16> %shuf2 to <4 x i32>76 %mul = mul <4 x i32> %zext1, %zext277 %ret = add <4 x i32> %mul, %val378 ret <4 x i32> %ret79}80 81; Test a v8i16 (odd) -> v4i32 unsigned widening multiply-and-add.82define <4 x i32> @f6(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {83; CHECK-LABEL: f6:84; CHECK: # %bb.0:85; CHECK-NEXT: vmaloh %v24, %v24, %v26, %v2886; CHECK-NEXT: br %r1487 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>88 %zext1 = zext <4 x i16> %shuf1 to <4 x i32>89 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>90 %zext2 = zext <4 x i16> %shuf2 to <4 x i32>91 %mul = mul <4 x i32> %zext1, %zext292 %ret = add <4 x i32> %mul, %val393 ret <4 x i32> %ret94}95 96; Test a v8i16 (even) -> v4i32 signed widening multiply-and-add.97define <4 x i32> @f7(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {98; CHECK-LABEL: f7:99; CHECK: # %bb.0:100; CHECK-NEXT: vmaeh %v24, %v24, %v26, %v28101; CHECK-NEXT: br %r14102 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>103 %sext1 = sext <4 x i16> %shuf1 to <4 x i32>104 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>105 %sext2 = sext <4 x i16> %shuf2 to <4 x i32>106 %mul = mul <4 x i32> %sext1, %sext2107 %ret = add <4 x i32> %mul, %val3108 ret <4 x i32> %ret109}110 111; Test a v8i16 (odd) -> v4i32 signed widening multiply-and-add.112define <4 x i32> @f8(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {113; CHECK-LABEL: f8:114; CHECK: # %bb.0:115; CHECK-NEXT: vmaoh %v24, %v24, %v26, %v28116; CHECK-NEXT: br %r14117 %shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>118 %sext1 = sext <4 x i16> %shuf1 to <4 x i32>119 %shuf2 = shufflevector <8 x i16> %val2, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>120 %sext2 = sext <4 x i16> %shuf2 to <4 x i32>121 %mul = mul <4 x i32> %sext1, %sext2122 %ret = add <4 x i32> %mul, %val3123 ret <4 x i32> %ret124}125 126; Test a v4i32 (even) -> v2i64 unsigned widening multiply-and-add.127define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {128; CHECK-LABEL: f9:129; CHECK: # %bb.0:130; CHECK-NEXT: vmalef %v24, %v24, %v26, %v28131; CHECK-NEXT: br %r14132 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>133 %zext1 = zext <2 x i32> %shuf1 to <2 x i64>134 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 0, i32 2>135 %zext2 = zext <2 x i32> %shuf2 to <2 x i64>136 %mul = mul <2 x i64> %zext1, %zext2137 %ret = add <2 x i64> %mul, %val3138 ret <2 x i64> %ret139}140 141; Test a v4i32 (odd) -> v2i64 unsigned widening multiply-and-add.142define <2 x i64> @f10(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {143; CHECK-LABEL: f10:144; CHECK: # %bb.0:145; CHECK-NEXT: vmalof %v24, %v24, %v26, %v28146; CHECK-NEXT: br %r14147 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>148 %zext1 = zext <2 x i32> %shuf1 to <2 x i64>149 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 1, i32 3>150 %zext2 = zext <2 x i32> %shuf2 to <2 x i64>151 %mul = mul <2 x i64> %zext1, %zext2152 %ret = add <2 x i64> %mul, %val3153 ret <2 x i64> %ret154}155 156; Test a v4i32 (even) -> v2i64 signed widening multiply-and-add.157define <2 x i64> @f11(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {158; CHECK-LABEL: f11:159; CHECK: # %bb.0:160; CHECK-NEXT: vmaef %v24, %v24, %v26, %v28161; CHECK-NEXT: br %r14162 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>163 %sext1 = sext <2 x i32> %shuf1 to <2 x i64>164 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 0, i32 2>165 %sext2 = sext <2 x i32> %shuf2 to <2 x i64>166 %mul = mul <2 x i64> %sext1, %sext2167 %ret = add <2 x i64> %mul, %val3168 ret <2 x i64> %ret169}170 171; Test a v4i32 (odd) -> v2i64 signed widening multiply-and-add.172define <2 x i64> @f12(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {173; CHECK-LABEL: f12:174; CHECK: # %bb.0:175; CHECK-NEXT: vmaof %v24, %v24, %v26, %v28176; CHECK-NEXT: br %r14177 %shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>178 %sext1 = sext <2 x i32> %shuf1 to <2 x i64>179 %shuf2 = shufflevector <4 x i32> %val2, <4 x i32> poison, <2 x i32> <i32 1, i32 3>180 %sext2 = sext <2 x i32> %shuf2 to <2 x i64>181 %mul = mul <2 x i64> %sext1, %sext2182 %ret = add <2 x i64> %mul, %val3183 ret <2 x i64> %ret184}185