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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test widening vector multiply-and-add on z17.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s5 6; Test a v2i64 (even) -> i128 unsigned widening multiply-and-add.7define i128 @f1(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vl %v0, 0(%r3), 311; CHECK-NEXT: vmaleg %v0, %v24, %v26, %v012; CHECK-NEXT: vst %v0, 0(%r2), 313; CHECK-NEXT: br %r1414 %elt1 = extractelement <2 x i64> %val1, i32 015 %zext1 = zext i64 %elt1 to i12816 %elt2 = extractelement <2 x i64> %val2, i32 017 %zext2 = zext i64 %elt2 to i12818 %mul = mul i128 %zext1, %zext219 %ret = add i128 %mul, %val320 ret i128 %ret21}22 23; Test a v2i64 (odd) -> i128 unsigned widening multiply-and-add.24define i128 @f2(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {25; CHECK-LABEL: f2:26; CHECK: # %bb.0:27; CHECK-NEXT: vl %v0, 0(%r3), 328; CHECK-NEXT: vmalog %v0, %v24, %v26, %v029; CHECK-NEXT: vst %v0, 0(%r2), 330; CHECK-NEXT: br %r1431 %elt1 = extractelement <2 x i64> %val1, i32 132 %zext1 = zext i64 %elt1 to i12833 %elt2 = extractelement <2 x i64> %val2, i32 134 %zext2 = zext i64 %elt2 to i12835 %mul = mul i128 %zext1, %zext236 %ret = add i128 %mul, %val337 ret i128 %ret38}39 40; Test a v2i64 (even) -> i128 signed widening multiply-and-add.41define i128 @f3(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {42; CHECK-LABEL: f3:43; CHECK: # %bb.0:44; CHECK-NEXT: vl %v0, 0(%r3), 345; CHECK-NEXT: vmaeg %v0, %v24, %v26, %v046; CHECK-NEXT: vst %v0, 0(%r2), 347; CHECK-NEXT: br %r1448 %elt1 = extractelement <2 x i64> %val1, i32 049 %sext1 = sext i64 %elt1 to i12850 %elt2 = extractelement <2 x i64> %val2, i32 051 %sext2 = sext i64 %elt2 to i12852 %mul = mul i128 %sext1, %sext253 %ret = add i128 %mul, %val354 ret i128 %ret55}56 57; Test a v2i64 (odd) -> i128 signed widening multiply-and-add.58define i128 @f4(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {59; CHECK-LABEL: f4:60; CHECK: # %bb.0:61; CHECK-NEXT: vl %v0, 0(%r3), 362; CHECK-NEXT: vmaog %v0, %v24, %v26, %v063; CHECK-NEXT: vst %v0, 0(%r2), 364; CHECK-NEXT: br %r1465 %elt1 = extractelement <2 x i64> %val1, i32 166 %sext1 = sext i64 %elt1 to i12867 %elt2 = extractelement <2 x i64> %val2, i32 168 %sext2 = sext i64 %elt2 to i12869 %mul = mul i128 %sext1, %sext270 %ret = add i128 %mul, %val371 ret i128 %ret72}73