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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; Test high-part vector multiply-and-add.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6; Test a v16i8 unsigned high-part multiply-and-add.7define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {8; CHECK-LABEL: f1:9; CHECK: # %bb.0:10; CHECK-NEXT: vmalhb %v24, %v24, %v26, %v2811; CHECK-NEXT: br %r1412 %zext1 = zext <16 x i8> %val1 to <16 x i16>13 %zext2 = zext <16 x i8> %val2 to <16 x i16>14 %zext3 = zext <16 x i8> %val3 to <16 x i16>15 %mulx = mul <16 x i16> %zext1, %zext216 %addx = add <16 x i16> %mulx, %zext317 %highx = lshr <16 x i16> %addx, splat(i16 8)18 %high = trunc <16 x i16> %highx to <16 x i8>19 ret <16 x i8> %high20}21 22; Test a v16i8 signed high-part multiply-and-add.23define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {24; CHECK-LABEL: f2:25; CHECK: # %bb.0:26; CHECK-NEXT: vmahb %v24, %v24, %v26, %v2827; CHECK-NEXT: br %r1428 %sext1 = sext <16 x i8> %val1 to <16 x i16>29 %sext2 = sext <16 x i8> %val2 to <16 x i16>30 %sext3 = sext <16 x i8> %val3 to <16 x i16>31 %mulx = mul <16 x i16> %sext1, %sext232 %addx = add <16 x i16> %mulx, %sext333 %highx = lshr <16 x i16> %addx, splat(i16 8)34 %high = trunc <16 x i16> %highx to <16 x i8>35 ret <16 x i8> %high36}37 38; Test a v8i16 unsigned high-part multiply-and-add.39define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {40; CHECK-LABEL: f3:41; CHECK: # %bb.0:42; CHECK-NEXT: vmalhh %v24, %v24, %v26, %v2843; CHECK-NEXT: br %r1444 %zext1 = zext <8 x i16> %val1 to <8 x i32>45 %zext2 = zext <8 x i16> %val2 to <8 x i32>46 %zext3 = zext <8 x i16> %val3 to <8 x i32>47 %mulx = mul <8 x i32> %zext1, %zext248 %addx = add <8 x i32> %mulx, %zext349 %highx = lshr <8 x i32> %addx, splat(i32 16)50 %high = trunc <8 x i32> %highx to <8 x i16>51 ret <8 x i16> %high52}53 54; Test a v8i16 signed high-part multiply-and-add.55define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {56; CHECK-LABEL: f4:57; CHECK: # %bb.0:58; CHECK-NEXT: vmahh %v24, %v24, %v26, %v2859; CHECK-NEXT: br %r1460 %sext1 = sext <8 x i16> %val1 to <8 x i32>61 %sext2 = sext <8 x i16> %val2 to <8 x i32>62 %sext3 = sext <8 x i16> %val3 to <8 x i32>63 %mulx = mul <8 x i32> %sext1, %sext264 %addx = add <8 x i32> %mulx, %sext365 %highx = lshr <8 x i32> %addx, splat(i32 16)66 %high = trunc <8 x i32> %highx to <8 x i16>67 ret <8 x i16> %high68}69 70; Test a v4i32 unsigned high-part multiply-and-add.71define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {72; CHECK-LABEL: f5:73; CHECK: # %bb.0:74; CHECK-NEXT: vmalhf %v24, %v24, %v26, %v2875; CHECK-NEXT: br %r1476 %zext1 = zext <4 x i32> %val1 to <4 x i64>77 %zext2 = zext <4 x i32> %val2 to <4 x i64>78 %zext3 = zext <4 x i32> %val3 to <4 x i64>79 %mulx = mul <4 x i64> %zext1, %zext280 %addx = add <4 x i64> %mulx, %zext381 %highx = lshr <4 x i64> %addx, splat(i64 32)82 %high = trunc <4 x i64> %highx to <4 x i32>83 ret <4 x i32> %high84}85 86; Test a v4i32 signed high-part multiply-and-add.87define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {88; CHECK-LABEL: f6:89; CHECK: # %bb.0:90; CHECK-NEXT: vmahf %v24, %v24, %v26, %v2891; CHECK-NEXT: br %r1492 %sext1 = sext <4 x i32> %val1 to <4 x i64>93 %sext2 = sext <4 x i32> %val2 to <4 x i64>94 %sext3 = sext <4 x i32> %val3 to <4 x i64>95 %mulx = mul <4 x i64> %sext1, %sext296 %addx = add <4 x i64> %mulx, %sext397 %highx = lshr <4 x i64> %addx, splat(i64 32)98 %high = trunc <4 x i64> %highx to <4 x i32>99 ret <4 x i32> %high100}101