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1; Test vector negation.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test a v16i8 negation.6define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val) {7; CHECK-LABEL: f1:8; CHECK: vlcb %v24, %v269; CHECK: br %r1410 %ret = sub <16 x i8> zeroinitializer, %val11 ret <16 x i8> %ret12}13 14; Test a v8i16 negation.15define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val) {16; CHECK-LABEL: f2:17; CHECK: vlch %v24, %v2618; CHECK: br %r1419 %ret = sub <8 x i16> zeroinitializer, %val20 ret <8 x i16> %ret21}22 23; Test a v4i32 negation.24define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val) {25; CHECK-LABEL: f3:26; CHECK: vlcf %v24, %v2627; CHECK: br %r1428 %ret = sub <4 x i32> zeroinitializer, %val29 ret <4 x i32> %ret30}31 32; Test a v2i64 negation.33define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val) {34; CHECK-LABEL: f4:35; CHECK: vlcg %v24, %v2636; CHECK: br %r1437 %ret = sub <2 x i64> zeroinitializer, %val38 ret <2 x i64> %ret39}40 41; Test a v2f64 negation.42define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val) {43; CHECK-LABEL: f5:44; CHECK: vflcdb %v24, %v2645; CHECK: br %r1446 %ret = fneg <2 x double> %val47 ret <2 x double> %ret48}49 50; Test an f64 negation that uses vector registers.51define double @f6(<2 x double> %val) {52; CHECK-LABEL: f6:53; CHECK: wflcdb %f0, %v2454; CHECK: br %r1455 %scalar = extractelement <2 x double> %val, i32 056 %ret = fneg double %scalar57 ret double %ret58}59