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1; Test vector merge high.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test a canonical v16i8 merge high.6define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {7; CHECK-LABEL: f1:8; CHECK: vmrhb %v24, %v24, %v269; CHECK: br %r1410 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,11 <16 x i32> <i32 0, i32 16, i32 1, i32 17,12 i32 2, i32 18, i32 3, i32 19,13 i32 4, i32 20, i32 5, i32 21,14 i32 6, i32 22, i32 7, i32 23>15 ret <16 x i8> %ret16}17 18; Test a reversed v16i8 merge high.19define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {20; CHECK-LABEL: f2:21; CHECK: vmrhb %v24, %v26, %v2422; CHECK: br %r1423 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,24 <16 x i32> <i32 16, i32 0, i32 17, i32 1,25 i32 18, i32 2, i32 19, i32 3,26 i32 20, i32 4, i32 21, i32 5,27 i32 22, i32 6, i32 23, i32 7>28 ret <16 x i8> %ret29}30 31; Test a v16i8 merge high with only the first operand being used.32define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {33; CHECK-LABEL: f3:34; CHECK: vmrhb %v24, %v24, %v2435; CHECK: br %r1436 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,37 <16 x i32> <i32 0, i32 0, i32 1, i32 1,38 i32 2, i32 2, i32 3, i32 3,39 i32 4, i32 4, i32 5, i32 5,40 i32 6, i32 6, i32 7, i32 7>41 ret <16 x i8> %ret42}43 44; Test a v16i8 merge high with only the second operand being used.45; This is converted into @f3 by target-independent code.46define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {47; CHECK-LABEL: f4:48; CHECK: vmrhb %v24, %v26, %v2649; CHECK: br %r1450 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,51 <16 x i32> <i32 16, i32 16, i32 17, i32 17,52 i32 18, i32 18, i32 19, i32 19,53 i32 20, i32 20, i32 21, i32 21,54 i32 22, i32 22, i32 23, i32 23>55 ret <16 x i8> %ret56}57 58; Test a v16i8 merge with both operands being the same. This too is59; converted into @f3 by target-independent code.60define <16 x i8> @f5(<16 x i8> %val) {61; CHECK-LABEL: f5:62; CHECK: vmrhb %v24, %v24, %v2463; CHECK: br %r1464 %ret = shufflevector <16 x i8> %val, <16 x i8> %val,65 <16 x i32> <i32 0, i32 16, i32 17, i32 17,66 i32 18, i32 2, i32 3, i32 3,67 i32 20, i32 20, i32 5, i32 5,68 i32 6, i32 22, i32 23, i32 7>69 ret <16 x i8> %ret70}71 72; Test a v16i8 merge in which some of the indices are don't care.73define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {74; CHECK-LABEL: f6:75; CHECK: vmrhb %v24, %v24, %v2676; CHECK: br %r1477 %ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,78 <16 x i32> <i32 0, i32 undef, i32 1, i32 17,79 i32 undef, i32 18, i32 undef, i32 undef,80 i32 undef, i32 20, i32 5, i32 21,81 i32 undef, i32 22, i32 7, i32 undef>82 ret <16 x i8> %ret83}84 85; Test a v16i8 merge in which one of the operands is undefined and where86; indices for that operand are "don't care". Target-independent code87; converts the indices themselves into "undef"s.88define <16 x i8> @f7(<16 x i8> %val) {89; CHECK-LABEL: f7:90; CHECK: vmrhb %v24, %v24, %v2491; CHECK: br %r1492 %ret = shufflevector <16 x i8> undef, <16 x i8> %val,93 <16 x i32> <i32 11, i32 16, i32 17, i32 5,94 i32 18, i32 10, i32 19, i32 19,95 i32 20, i32 20, i32 21, i32 3,96 i32 2, i32 22, i32 9, i32 23>97 ret <16 x i8> %ret98}99 100; Test a canonical v8i16 merge high.101define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {102; CHECK-LABEL: f8:103; CHECK: vmrhh %v24, %v24, %v26104; CHECK: br %r14105 %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,106 <8 x i32> <i32 0, i32 8, i32 1, i32 9,107 i32 2, i32 10, i32 3, i32 11>108 ret <8 x i16> %ret109}110 111; Test a reversed v8i16 merge high.112define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) {113; CHECK-LABEL: f9:114; CHECK: vmrhh %v24, %v26, %v24115; CHECK: br %r14116 %ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,117 <8 x i32> <i32 8, i32 0, i32 9, i32 1,118 i32 10, i32 2, i32 11, i32 3>119 ret <8 x i16> %ret120}121 122; Test a canonical v4i32 merge high.123define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) {124; CHECK-LABEL: f10:125; CHECK: vmrhf %v24, %v24, %v26126; CHECK: br %r14127 %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,128 <4 x i32> <i32 0, i32 4, i32 1, i32 5>129 ret <4 x i32> %ret130}131 132; Test a reversed v4i32 merge high.133define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) {134; CHECK-LABEL: f11:135; CHECK: vmrhf %v24, %v26, %v24136; CHECK: br %r14137 %ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,138 <4 x i32> <i32 4, i32 0, i32 5, i32 1>139 ret <4 x i32> %ret140}141 142; Test a canonical v2i64 merge high.143define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2) {144; CHECK-LABEL: f12:145; CHECK: vmrhg %v24, %v24, %v26146; CHECK: br %r14147 %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,148 <2 x i32> <i32 0, i32 2>149 ret <2 x i64> %ret150}151 152; Test a reversed v2i64 merge high.153define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) {154; CHECK-LABEL: f13:155; CHECK: vmrhg %v24, %v26, %v24156; CHECK: br %r14157 %ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,158 <2 x i32> <i32 2, i32 0>159 ret <2 x i64> %ret160}161 162; Test a canonical v4f32 merge high.163define <4 x float> @f14(<4 x float> %val1, <4 x float> %val2) {164; CHECK-LABEL: f14:165; CHECK: vmrhf %v24, %v24, %v26166; CHECK: br %r14167 %ret = shufflevector <4 x float> %val1, <4 x float> %val2,168 <4 x i32> <i32 0, i32 4, i32 1, i32 5>169 ret <4 x float> %ret170}171 172; Test a reversed v4f32 merge high.173define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2) {174; CHECK-LABEL: f15:175; CHECK: vmrhf %v24, %v26, %v24176; CHECK: br %r14177 %ret = shufflevector <4 x float> %val1, <4 x float> %val2,178 <4 x i32> <i32 4, i32 0, i32 5, i32 1>179 ret <4 x float> %ret180}181 182; Test a canonical v2f64 merge high.183define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) {184; CHECK-LABEL: f16:185; CHECK: vmrhg %v24, %v24, %v26186; CHECK: br %r14187 %ret = shufflevector <2 x double> %val1, <2 x double> %val2,188 <2 x i32> <i32 0, i32 2>189 ret <2 x double> %ret190}191 192; Test a reversed v2f64 merge high.193define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) {194; CHECK-LABEL: f17:195; CHECK: vmrhg %v24, %v26, %v24196; CHECK: br %r14197 %ret = shufflevector <2 x double> %val1, <2 x double> %val2,198 <2 x i32> <i32 2, i32 0>199 ret <2 x double> %ret200}201