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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; Test vector add reduction intrinsic3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s5 6; 1 vector length7declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %a)8declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %a)9declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)10declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a)11declare i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)12; 2 vector lengths13declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %a)14declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %a)15declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %a)16declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %a)17declare i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)18; ; TODO19; ; 4 vector lengths20declare i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %a)21declare i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %a)22declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)23declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %a)24declare i128 @llvm.vector.reduce.add.v4i128(<4 x i128> %a)25; ; Subvector lengths26declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a)27declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a)28declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %a)29declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)30 31define i8 @f1_1(<16 x i8> %a) {32; CHECK-LABEL: f1_1:33; CHECK: # %bb.0:34; CHECK-NEXT: vgbm %v0, 035; CHECK-NEXT: vsumb %v1, %v24, %v036; CHECK-NEXT: vsumqf %v0, %v1, %v037; CHECK-NEXT: vlgvf %r2, %v0, 338; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d39; CHECK-NEXT: br %r1440 %redadd = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %a)41 ret i8 %redadd42}43 44define i16 @f1_2(<8 x i16> %a) {45; CHECK-LABEL: f1_2:46; CHECK: # %bb.0:47; CHECK-NEXT: vgbm %v0, 048; CHECK-NEXT: vsumh %v1, %v24, %v049; CHECK-NEXT: vsumqf %v0, %v1, %v050; CHECK-NEXT: vlgvf %r2, %v0, 351; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d52; CHECK-NEXT: br %r1453 %redadd = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %a)54 ret i16 %redadd55}56 57define i32 @f1_3(<4 x i32> %a) {58; CHECK-LABEL: f1_3:59; CHECK: # %bb.0:60; CHECK-NEXT: vgbm %v0, 061; CHECK-NEXT: vsumqf %v0, %v24, %v062; CHECK-NEXT: vlgvf %r2, %v0, 363; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d64; CHECK-NEXT: br %r1465 66 %redadd = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)67 ret i32 %redadd68}69 70define i64 @f1_4(<2 x i64> %a) {71; CHECK-LABEL: f1_4:72; CHECK: # %bb.0:73; CHECK-NEXT: vrepg %v0, %v24, 174; CHECK-NEXT: vag %v0, %v24, %v075; CHECK-NEXT: vlgvg %r2, %v0, 076; CHECK-NEXT: br %r1477 78 %redadd = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a)79 ret i64 %redadd80}81 82define i128 @f1_5(<1 x i128> %a) {83; CHECK-LABEL: f1_5:84; CHECK: # %bb.0:85; CHECK-NEXT: vst %v24, 0(%r2), 386; CHECK-NEXT: br %r1487 %redadd = call i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)88 ret i128 %redadd89}90 91define i8 @f2_1(<32 x i8> %a) {92; CHECK-LABEL: f2_1:93; CHECK: # %bb.0:94; CHECK-NEXT: vab %v0, %v24, %v2695; CHECK-NEXT: vgbm %v1, 096; CHECK-NEXT: vsumb %v0, %v0, %v197; CHECK-NEXT: vsumqf %v0, %v0, %v198; CHECK-NEXT: vlgvf %r2, %v0, 399; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d100; CHECK-NEXT: br %r14101 %redadd = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %a)102 ret i8 %redadd103}104 105define i16 @f2_2(<16 x i16> %a) {106; CHECK-LABEL: f2_2:107; CHECK: # %bb.0:108; CHECK-NEXT: vah %v0, %v24, %v26109; CHECK-NEXT: vgbm %v1, 0110; CHECK-NEXT: vsumh %v0, %v0, %v1111; CHECK-NEXT: vsumqf %v0, %v0, %v1112; CHECK-NEXT: vlgvf %r2, %v0, 3113; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d114; CHECK-NEXT: br %r14115 %redadd = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %a)116 ret i16 %redadd117}118 119define i32 @f2_3(<8 x i32> %a) {120; CHECK-LABEL: f2_3:121; CHECK: # %bb.0:122; CHECK-NEXT: vaf %v0, %v24, %v26123; CHECK-NEXT: vgbm %v1, 0124; CHECK-NEXT: vsumqf %v0, %v0, %v1125; CHECK-NEXT: vlgvf %r2, %v0, 3126; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d127; CHECK-NEXT: br %r14128 129 %redadd = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %a)130 ret i32 %redadd131}132 133define i64 @f2_4(<4 x i64> %a) {134; CHECK-LABEL: f2_4:135; CHECK: # %bb.0:136; CHECK-NEXT: vag %v0, %v24, %v26137; CHECK-NEXT: vrepg %v1, %v0, 1138; CHECK-NEXT: vag %v0, %v0, %v1139; CHECK-NEXT: vlgvg %r2, %v0, 0140; CHECK-NEXT: br %r14141 142 %redadd = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %a)143 ret i64 %redadd144}145 146define i128 @f2_5(<2 x i128> %a) {147; CHECK-LABEL: f2_5:148; CHECK: # %bb.0:149; CHECK-NEXT: vl %v0, 16(%r3), 3150; CHECK-NEXT: vl %v1, 0(%r3), 3151; CHECK-NEXT: vaq %v0, %v1, %v0152; CHECK-NEXT: vst %v0, 0(%r2), 3153; CHECK-NEXT: br %r14154 %redadd = call i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)155 ret i128 %redadd156}157 158define i8 @f3_1(<64 x i8> %a) {159; CHECK-LABEL: f3_1:160; CHECK: # %bb.0:161; CHECK-NEXT: vab %v0, %v26, %v30162; CHECK-NEXT: vab %v1, %v24, %v28163; CHECK-NEXT: vab %v0, %v1, %v0164; CHECK-NEXT: vgbm %v1, 0165; CHECK-NEXT: vsumb %v0, %v0, %v1166; CHECK-NEXT: vsumqf %v0, %v0, %v1167; CHECK-NEXT: vlgvf %r2, %v0, 3168; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d169; CHECK-NEXT: br %r14170 %redadd = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %a)171 ret i8 %redadd172}173 174define i16 @f3_2(<32 x i16> %a) {175; CHECK-LABEL: f3_2:176; CHECK: # %bb.0:177; CHECK-NEXT: vah %v0, %v26, %v30178; CHECK-NEXT: vah %v1, %v24, %v28179; CHECK-NEXT: vah %v0, %v1, %v0180; CHECK-NEXT: vgbm %v1, 0181; CHECK-NEXT: vsumh %v0, %v0, %v1182; CHECK-NEXT: vsumqf %v0, %v0, %v1183; CHECK-NEXT: vlgvf %r2, %v0, 3184; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d185; CHECK-NEXT: br %r14186 %redadd = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %a)187 ret i16 %redadd188}189 190define i32 @f3_3(<16 x i32> %a) {191; CHECK-LABEL: f3_3:192; CHECK: # %bb.0:193; CHECK-NEXT: vaf %v0, %v26, %v30194; CHECK-NEXT: vaf %v1, %v24, %v28195; CHECK-NEXT: vaf %v0, %v1, %v0196; CHECK-NEXT: vgbm %v1, 0197; CHECK-NEXT: vsumqf %v0, %v0, %v1198; CHECK-NEXT: vlgvf %r2, %v0, 3199; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d200; CHECK-NEXT: br %r14201 202 %redadd = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)203 ret i32 %redadd204}205 206define i64 @f3_4(<8 x i64> %a) {207; CHECK-LABEL: f3_4:208; CHECK: # %bb.0:209; CHECK-NEXT: vag %v0, %v26, %v30210; CHECK-NEXT: vag %v1, %v24, %v28211; CHECK-NEXT: vag %v0, %v1, %v0212; CHECK-NEXT: vrepg %v1, %v0, 1213; CHECK-NEXT: vag %v0, %v0, %v1214; CHECK-NEXT: vlgvg %r2, %v0, 0215; CHECK-NEXT: br %r14216 217 %redadd = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %a)218 ret i64 %redadd219}220 221define i128 @f3_5(<4 x i128> %a) {222; CHECK-LABEL: f3_5:223; CHECK: # %bb.0:224; CHECK-NEXT: vl %v0, 32(%r3), 3225; CHECK-NEXT: vl %v1, 0(%r3), 3226; CHECK-NEXT: vl %v2, 48(%r3), 3227; CHECK-NEXT: vl %v3, 16(%r3), 3228; CHECK-NEXT: vaq %v2, %v3, %v2229; CHECK-NEXT: vaq %v0, %v1, %v0230; CHECK-NEXT: vaq %v0, %v0, %v2231; CHECK-NEXT: vst %v0, 0(%r2), 3232; CHECK-NEXT: br %r14233 %redadd = call i128 @llvm.vector.reduce.add.v4i128(<4 x i128> %a)234 ret i128 %redadd235}236 237 238define i8 @f4_1(<8 x i8> %a) {239; CHECK-LABEL: f4_1:240; CHECK: # %bb.0:241; CHECK-NEXT: vpkg %v0, %v24, %v24242; CHECK-NEXT: vab %v0, %v24, %v0243; CHECK-NEXT: vpkf %v1, %v0, %v0244; CHECK-NEXT: vab %v0, %v0, %v1245; CHECK-NEXT: vrepb %v1, %v0, 1246; CHECK-NEXT: vab %v0, %v0, %v1247; CHECK-NEXT: vlgvb %r2, %v0, 0248; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d249; CHECK-NEXT: br %r14250 %redadd = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a)251 ret i8 %redadd252}253 254define i16 @f4_2(<4 x i16> %a) {255; CHECK-LABEL: f4_2:256; CHECK: # %bb.0:257; CHECK-NEXT: vpkg %v0, %v24, %v24258; CHECK-NEXT: vah %v0, %v24, %v0259; CHECK-NEXT: vreph %v1, %v0, 1260; CHECK-NEXT: vah %v0, %v0, %v1261; CHECK-NEXT: vlgvh %r2, %v0, 0262; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d263; CHECK-NEXT: br %r14264 %redadd = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a)265 ret i16 %redadd266}267 268define i32 @f4_3(<2 x i32> %a) {269; CHECK-LABEL: f4_3:270; CHECK: # %bb.0:271; CHECK-NEXT: vrepf %v0, %v24, 1272; CHECK-NEXT: vaf %v0, %v24, %v0273; CHECK-NEXT: vlgvf %r2, %v0, 0274; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d275; CHECK-NEXT: br %r14276 277 %redadd = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %a)278 ret i32 %redadd279}280 281define i64 @f4_4(<1 x i64> %a) {282; CHECK-LABEL: f4_4:283; CHECK: # %bb.0:284; CHECK-NEXT: vlgvg %r2, %v24, 0285; CHECK-NEXT: br %r14286 287 %redadd = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)288 ret i64 %redadd289}290