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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Test vector rotate left instructions with vector rotate amount.3;4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s5 6declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)7declare <8 x i16> @llvm.fshl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)8declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)9declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)10 11; Test a v16i8 rotate left.12define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val, <16 x i8> %amt) {13; CHECK-LABEL: f1:14; CHECK: # %bb.0:15; CHECK-NEXT: verllvb %v24, %v26, %v2816; CHECK-NEXT: br %r1417 18 %inv = sub <16 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8,19 i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>, %amt20 %parta = shl <16 x i8> %val, %amt21 %partb = lshr <16 x i8> %val, %inv22 23 %rotl = or <16 x i8> %parta, %partb24 25 ret <16 x i8> %rotl26}27 28; Test a v16i8 rotate left (matched from fshl).29define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val, <16 x i8> %amt) {30; CHECK-LABEL: f2:31; CHECK: # %bb.0:32; CHECK-NEXT: verllvb %v24, %v26, %v2833; CHECK-NEXT: br %r1434 35 %rotl = tail call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %val, <16 x i8> %val, <16 x i8> %amt)36 37 ret <16 x i8> %rotl38}39 40; Test a v8i16 rotate left.41define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val, <8 x i16> %amt) {42; CHECK-LABEL: f3:43; CHECK: # %bb.0:44; CHECK-NEXT: verllvh %v24, %v26, %v2845; CHECK-NEXT: br %r1446 47 %inv = sub <8 x i16> <i16 16, i16 16, i16 16, i16 16,48 i16 16, i16 16, i16 16, i16 16>, %amt49 %parta = shl <8 x i16> %val, %amt50 %partb = lshr <8 x i16> %val, %inv51 52 %rotl = or <8 x i16> %parta, %partb53 54 ret <8 x i16> %rotl55}56 57; Test a v8i16 rotate left (matched from fshl).58define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val, <8 x i16> %amt) {59; CHECK-LABEL: f4:60; CHECK: # %bb.0:61; CHECK-NEXT: verllvh %v24, %v26, %v2862; CHECK-NEXT: br %r1463 64 %rotl = tail call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %val, <8 x i16> %val, <8 x i16> %amt)65 66 ret <8 x i16> %rotl67}68 69; Test a v4i32 rotate left.70define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val, <4 x i32> %amt) {71; CHECK-LABEL: f5:72; CHECK: # %bb.0:73; CHECK-NEXT: verllvf %v24, %v26, %v2874; CHECK-NEXT: br %r1475 76 %inv = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %amt77 %parta = shl <4 x i32> %val, %amt78 %partb = lshr <4 x i32> %val, %inv79 80 %rotl = or <4 x i32> %parta, %partb81 82 ret <4 x i32> %rotl83}84 85; Test a v4i32 rotate left (matched from fshl).86define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val, <4 x i32> %amt) {87; CHECK-LABEL: f6:88; CHECK: # %bb.0:89; CHECK-NEXT: verllvf %v24, %v26, %v2890; CHECK-NEXT: br %r1491 92 %rotl = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %val, <4 x i32> %val, <4 x i32> %amt)93 94 ret <4 x i32> %rotl95}96 97; Test a v2i64 rotate left.98define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val, <2 x i64> %amt) {99; CHECK-LABEL: f7:100; CHECK: # %bb.0:101; CHECK-NEXT: verllvg %v24, %v26, %v28102; CHECK-NEXT: br %r14103 104 %inv = sub <2 x i64> <i64 64, i64 64>, %amt105 %parta = shl <2 x i64> %val, %amt106 %partb = lshr <2 x i64> %val, %inv107 108 %rotl = or <2 x i64> %parta, %partb109 110 ret <2 x i64> %rotl111}112 113; Test a v2i64 rotate left (matched from fshl).114define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val, <2 x i64> %amt) {115; CHECK-LABEL: f8:116; CHECK: # %bb.0:117; CHECK-NEXT: verllvg %v24, %v26, %v28118; CHECK-NEXT: br %r14119 120 %rotl = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %val, <2 x i64> %val, <2 x i64> %amt)121 122 ret <2 x i64> %rotl123}124