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1; Test vector sign extensions.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test a v16i1->v16i8 extension.6define <16 x i8> @f1(<16 x i8> %val) {7; CHECK-LABEL: f1:8; CHECK: veslb [[REG:%v[0-9]+]], %v24, 79; CHECK: vesrab %v24, [[REG]], 710; CHECK: br %r1411 %trunc = trunc <16 x i8> %val to <16 x i1>12 %ret = sext <16 x i1> %trunc to <16 x i8>13 ret <16 x i8> %ret14}15 16; Test a v8i1->v8i16 extension.17define <8 x i16> @f2(<8 x i16> %val) {18; CHECK-LABEL: f2:19; CHECK: veslh [[REG:%v[0-9]+]], %v24, 1520; CHECK: vesrah %v24, [[REG]], 1521; CHECK: br %r1422 %trunc = trunc <8 x i16> %val to <8 x i1>23 %ret = sext <8 x i1> %trunc to <8 x i16>24 ret <8 x i16> %ret25}26 27; Test a v8i8->v8i16 extension.28define <8 x i16> @f3(<8 x i16> %val) {29; CHECK-LABEL: f3:30; CHECK: veslh [[REG:%v[0-9]+]], %v24, 831; CHECK: vesrah %v24, [[REG]], 832; CHECK: br %r1433 %trunc = trunc <8 x i16> %val to <8 x i8>34 %ret = sext <8 x i8> %trunc to <8 x i16>35 ret <8 x i16> %ret36}37 38; Test a v4i1->v4i32 extension.39define <4 x i32> @f4(<4 x i32> %val) {40; CHECK-LABEL: f4:41; CHECK: veslf [[REG:%v[0-9]+]], %v24, 3142; CHECK: vesraf %v24, [[REG]], 3143; CHECK: br %r1444 %trunc = trunc <4 x i32> %val to <4 x i1>45 %ret = sext <4 x i1> %trunc to <4 x i32>46 ret <4 x i32> %ret47}48 49; Test a v4i8->v4i32 extension.50define <4 x i32> @f5(<4 x i32> %val) {51; CHECK-LABEL: f5:52; CHECK: veslf [[REG:%v[0-9]+]], %v24, 2453; CHECK: vesraf %v24, [[REG]], 2454; CHECK: br %r1455 %trunc = trunc <4 x i32> %val to <4 x i8>56 %ret = sext <4 x i8> %trunc to <4 x i32>57 ret <4 x i32> %ret58}59 60; Test a v4i16->v4i32 extension.61define <4 x i32> @f6(<4 x i32> %val) {62; CHECK-LABEL: f6:63; CHECK: veslf [[REG:%v[0-9]+]], %v24, 1664; CHECK: vesraf %v24, [[REG]], 1665; CHECK: br %r1466 %trunc = trunc <4 x i32> %val to <4 x i16>67 %ret = sext <4 x i16> %trunc to <4 x i32>68 ret <4 x i32> %ret69}70 71; Test a v2i1->v2i64 extension.72define <2 x i64> @f7(<2 x i64> %val) {73; CHECK-LABEL: f7:74; CHECK: veslg [[REG:%v[0-9]+]], %v24, 6375; CHECK: vesrag %v24, [[REG]], 6376; CHECK: br %r1477 %trunc = trunc <2 x i64> %val to <2 x i1>78 %ret = sext <2 x i1> %trunc to <2 x i64>79 ret <2 x i64> %ret80}81 82; Test a v2i8->v2i64 extension.83define <2 x i64> @f8(<2 x i64> %val) {84; CHECK-LABEL: f8:85; CHECK: vsegb %v24, %v2486; CHECK: br %r1487 %trunc = trunc <2 x i64> %val to <2 x i8>88 %ret = sext <2 x i8> %trunc to <2 x i64>89 ret <2 x i64> %ret90}91 92; Test a v2i16->v2i64 extension.93define <2 x i64> @f9(<2 x i64> %val) {94; CHECK-LABEL: f9:95; CHECK: vsegh %v24, %v2496; CHECK: br %r1497 %trunc = trunc <2 x i64> %val to <2 x i16>98 %ret = sext <2 x i16> %trunc to <2 x i64>99 ret <2 x i64> %ret100}101 102; Test a v2i32->v2i64 extension.103define <2 x i64> @f10(<2 x i64> %val) {104; CHECK-LABEL: f10:105; CHECK: vsegf %v24, %v24106; CHECK: br %r14107 %trunc = trunc <2 x i64> %val to <2 x i32>108 %ret = sext <2 x i32> %trunc to <2 x i64>109 ret <2 x i64> %ret110}111 112; Test an alternative v2i8->v2i64 extension.113define <2 x i64> @f11(<2 x i64> %val) {114; CHECK-LABEL: f11:115; CHECK: vsegb %v24, %v24116; CHECK: br %r14117 %shl = shl <2 x i64> %val, <i64 56, i64 56>118 %ret = ashr <2 x i64> %shl, <i64 56, i64 56>119 ret <2 x i64> %ret120}121 122; Test an alternative v2i16->v2i64 extension.123define <2 x i64> @f12(<2 x i64> %val) {124; CHECK-LABEL: f12:125; CHECK: vsegh %v24, %v24126; CHECK: br %r14127 %shl = shl <2 x i64> %val, <i64 48, i64 48>128 %ret = ashr <2 x i64> %shl, <i64 48, i64 48>129 ret <2 x i64> %ret130}131 132; Test an alternative v2i32->v2i64 extension.133define <2 x i64> @f13(<2 x i64> %val) {134; CHECK-LABEL: f13:135; CHECK: vsegf %v24, %v24136; CHECK: br %r14137 %shl = shl <2 x i64> %val, <i64 32, i64 32>138 %ret = ashr <2 x i64> %shl, <i64 32, i64 32>139 ret <2 x i64> %ret140}141 142; Test an extraction-based v2i8->v2i64 extension.143define <2 x i64> @f14(<16 x i8> %val) {144; CHECK-LABEL: f14:145; CHECK: vsegb %v24, %v24146; CHECK: br %r14147 %elt0 = extractelement <16 x i8> %val, i32 7148 %elt1 = extractelement <16 x i8> %val, i32 15149 %ext0 = sext i8 %elt0 to i64150 %ext1 = sext i8 %elt1 to i64151 %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0152 %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1153 ret <2 x i64> %vec1154}155 156; Test an extraction-based v2i16->v2i64 extension.157define <2 x i64> @f15(<16 x i16> %val) {158; CHECK-LABEL: f15:159; CHECK: vsegh %v24, %v24160; CHECK: br %r14161 %elt0 = extractelement <16 x i16> %val, i32 3162 %elt1 = extractelement <16 x i16> %val, i32 7163 %ext0 = sext i16 %elt0 to i64164 %ext1 = sext i16 %elt1 to i64165 %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0166 %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1167 ret <2 x i64> %vec1168}169 170; Test an extraction-based v2i32->v2i64 extension.171define <2 x i64> @f16(<16 x i32> %val) {172; CHECK-LABEL: f16:173; CHECK: vsegf %v24, %v24174; CHECK: br %r14175 %elt0 = extractelement <16 x i32> %val, i32 1176 %elt1 = extractelement <16 x i32> %val, i32 3177 %ext0 = sext i32 %elt0 to i64178 %ext1 = sext i32 %elt1 to i64179 %vec0 = insertelement <2 x i64> undef, i64 %ext0, i32 0180 %vec1 = insertelement <2 x i64> %vec0, i64 %ext1, i32 1181 ret <2 x i64> %vec1182}183 184; Test a shufflevector-based v2i8->v2i64 extension.185define <2 x i64> @f17(<16 x i8> %val) {186; CHECK-LABEL: f17:187; CHECK: vsegb %v24, %v24188; CHECK: br %r14189 %shuf = shufflevector <16 x i8> %val, <16 x i8> poison, <2 x i32> <i32 7, i32 15>190 %ret = sext <2 x i8> %shuf to <2 x i64>191 ret <2 x i64> %ret192}193 194; Test a shufflevector-based v2i16->v2i64 extension.195define <2 x i64> @f18(<8 x i16> %val) {196; CHECK-LABEL: f18:197; CHECK: vsegh %v24, %v24198; CHECK: br %r14199 %shuf = shufflevector <8 x i16> %val, <8 x i16> poison, <2 x i32> <i32 3, i32 7>200 %ret = sext <2 x i16> %shuf to <2 x i64>201 ret <2 x i64> %ret202}203 204; Test a shufflevector-based v2i32->v2i64 extension.205define <2 x i64> @f19(<4 x i32> %val) {206; CHECK-LABEL: f19:207; CHECK: vsegf %v24, %v24208; CHECK: br %r14209 %shuf = shufflevector <4 x i32> %val, <4 x i32> poison, <2 x i32> <i32 1, i32 3>210 %ret = sext <2 x i32> %shuf to <2 x i64>211 ret <2 x i64> %ret212}213