561 lines · plain
1; Test strict v4f32 comparisons.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test oeq.6define <4 x i32> @f1(<4 x float> %val1, <4 x float> %val2) #0 {7; CHECK-LABEL: f1:8; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v249; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v2410; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v2611; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v2612; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]13; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]14; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]15; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]16; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]17; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]18; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]19; CHECK-NEXT: br %r1420 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(21 <4 x float> %val1, <4 x float> %val2,22 metadata !"oeq",23 metadata !"fpexcept.strict") #024 %ret = sext <4 x i1> %cmp to <4 x i32>25 ret <4 x i32> %ret26}27 28; Test one.29define <4 x i32> @f2(<4 x float> %val1, <4 x float> %val2) #0 {30; CHECK-LABEL: f2:31; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v2432; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v2433; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v2634; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v2635; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]36; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]37; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]38; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]39; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]40; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]41; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]42; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]43; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]44; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]45; CHECK: vo %v24, [[RES1]], [[RES0]]46; CHECK-NEXT: br %r1447 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(48 <4 x float> %val1, <4 x float> %val2,49 metadata !"one",50 metadata !"fpexcept.strict") #051 %ret = sext <4 x i1> %cmp to <4 x i32>52 ret <4 x i32> %ret53}54 55; Test ogt.56define <4 x i32> @f3(<4 x float> %val1, <4 x float> %val2) #0 {57; CHECK-LABEL: f3:58; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v2459; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v2460; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v2661; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v2662; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]63; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]64; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]65; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]66; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]67; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]68; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]69; CHECK-NEXT: br %r1470 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(71 <4 x float> %val1, <4 x float> %val2,72 metadata !"ogt",73 metadata !"fpexcept.strict") #074 %ret = sext <4 x i1> %cmp to <4 x i32>75 ret <4 x i32> %ret76}77 78; Test oge.79define <4 x i32> @f4(<4 x float> %val1, <4 x float> %val2) #0 {80; CHECK-LABEL: f4:81; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v2482; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v2483; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v2684; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v2685; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]86; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]87; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]88; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]89; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]90; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]91; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]92; CHECK-NEXT: br %r1493 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(94 <4 x float> %val1, <4 x float> %val2,95 metadata !"oge",96 metadata !"fpexcept.strict") #097 %ret = sext <4 x i1> %cmp to <4 x i32>98 ret <4 x i32> %ret99}100 101; Test ole.102define <4 x i32> @f5(<4 x float> %val1, <4 x float> %val2) #0 {103; CHECK-LABEL: f5:104; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24105; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24106; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26107; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26108; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]109; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]110; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]111; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]112; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]113; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]114; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]115; CHECK-NEXT: br %r14116 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(117 <4 x float> %val1, <4 x float> %val2,118 metadata !"ole",119 metadata !"fpexcept.strict") #0120 %ret = sext <4 x i1> %cmp to <4 x i32>121 ret <4 x i32> %ret122}123 124; Test olt.125define <4 x i32> @f6(<4 x float> %val1, <4 x float> %val2) #0 {126; CHECK-LABEL: f6:127; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24128; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24129; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26130; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26131; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]132; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]133; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]134; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]135; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]136; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]137; CHECK: vpkg %v24, [[HIGHRES]], [[LOWRES]]138; CHECK-NEXT: br %r14139 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(140 <4 x float> %val1, <4 x float> %val2,141 metadata !"olt",142 metadata !"fpexcept.strict") #0143 %ret = sext <4 x i1> %cmp to <4 x i32>144 ret <4 x i32> %ret145}146 147; Test ueq.148define <4 x i32> @f7(<4 x float> %val1, <4 x float> %val2) #0 {149; CHECK-LABEL: f7:150; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24151; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24152; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26153; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26154; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]155; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]156; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]157; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]158; CHECK-DAG: vfchdb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]159; CHECK-DAG: vfchdb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]160; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]161; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]162; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]163; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]164; CHECK: vno %v24, [[RES1]], [[RES0]]165; CHECK-NEXT: br %r14166 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(167 <4 x float> %val1, <4 x float> %val2,168 metadata !"ueq",169 metadata !"fpexcept.strict") #0170 %ret = sext <4 x i1> %cmp to <4 x i32>171 ret <4 x i32> %ret172}173 174; Test une.175define <4 x i32> @f8(<4 x float> %val1, <4 x float> %val2) #0 {176; CHECK-LABEL: f8:177; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24178; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24179; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26180; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26181; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]182; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]183; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]184; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]185; CHECK-DAG: vfcedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]186; CHECK-DAG: vfcedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]187; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]188; CHECK-NEXT: vno %v24, [[RES]], [[RES]]189; CHECK-NEXT: br %r14190 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(191 <4 x float> %val1, <4 x float> %val2,192 metadata !"une",193 metadata !"fpexcept.strict") #0194 %ret = sext <4 x i1> %cmp to <4 x i32>195 ret <4 x i32> %ret196}197 198; Test ugt.199define <4 x i32> @f9(<4 x float> %val1, <4 x float> %val2) #0 {200; CHECK-LABEL: f9:201; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24202; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24203; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26204; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26205; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]206; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]207; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]208; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]209; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]210; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]211; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]212; CHECK-NEXT: vno %v24, [[RES]], [[RES]]213; CHECK-NEXT: br %r14214 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(215 <4 x float> %val1, <4 x float> %val2,216 metadata !"ugt",217 metadata !"fpexcept.strict") #0218 %ret = sext <4 x i1> %cmp to <4 x i32>219 ret <4 x i32> %ret220}221 222; Test uge.223define <4 x i32> @f10(<4 x float> %val1, <4 x float> %val2) #0 {224; CHECK-LABEL: f10:225; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24226; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24227; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26228; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26229; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]230; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]231; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]232; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]233; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]234; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW1D]], [[LOW0D]]235; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]236; CHECK-NEXT: vno %v24, [[RES]], [[RES]]237; CHECK-NEXT: br %r14238 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(239 <4 x float> %val1, <4 x float> %val2,240 metadata !"uge",241 metadata !"fpexcept.strict") #0242 %ret = sext <4 x i1> %cmp to <4 x i32>243 ret <4 x i32> %ret244}245 246; Test ule.247define <4 x i32> @f11(<4 x float> %val1, <4 x float> %val2) #0 {248; CHECK-LABEL: f11:249; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24250; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24251; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26252; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26253; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]254; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]255; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]256; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]257; CHECK-DAG: vfchdb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]258; CHECK-DAG: vfchdb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]259; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]260; CHECK-NEXT: vno %v24, [[RES]], [[RES]]261; CHECK-NEXT: br %r14262 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(263 <4 x float> %val1, <4 x float> %val2,264 metadata !"ule",265 metadata !"fpexcept.strict") #0266 %ret = sext <4 x i1> %cmp to <4 x i32>267 ret <4 x i32> %ret268}269 270; Test ult.271define <4 x i32> @f12(<4 x float> %val1, <4 x float> %val2) #0 {272; CHECK-LABEL: f12:273; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24274; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24275; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26276; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26277; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]278; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]279; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]280; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]281; CHECK-DAG: vfchedb [[HIGHRES:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]282; CHECK-DAG: vfchedb [[LOWRES:%v[0-9]+]], [[LOW0D]], [[LOW1D]]283; CHECK: vpkg [[RES:%v[0-9]+]], [[HIGHRES]], [[LOWRES]]284; CHECK-NEXT: vno %v24, [[RES]], [[RES]]285; CHECK-NEXT: br %r14286 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(287 <4 x float> %val1, <4 x float> %val2,288 metadata !"ult",289 metadata !"fpexcept.strict") #0290 %ret = sext <4 x i1> %cmp to <4 x i32>291 ret <4 x i32> %ret292}293 294; Test ord.295define <4 x i32> @f13(<4 x float> %val1, <4 x float> %val2) #0 {296; CHECK-LABEL: f13:297; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24298; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24299; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26300; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26301; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]302; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]303; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]304; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]305; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]306; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]307; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]308; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]309; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]310; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]311; CHECK: vo %v24, [[RES1]], [[RES0]]312; CHECK-NEXT: br %r14313 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(314 <4 x float> %val1, <4 x float> %val2,315 metadata !"ord",316 metadata !"fpexcept.strict") #0317 %ret = sext <4 x i1> %cmp to <4 x i32>318 ret <4 x i32> %ret319}320 321; Test uno.322define <4 x i32> @f14(<4 x float> %val1, <4 x float> %val2) #0 {323; CHECK-LABEL: f14:324; CHECK-DAG: vmrhf [[HIGH0E:%v[0-9]+]], %v24, %v24325; CHECK-DAG: vmrlf [[LOW0E:%v[0-9]+]], %v24, %v24326; CHECK-DAG: vmrhf [[HIGH1E:%v[0-9]+]], %v26, %v26327; CHECK-DAG: vmrlf [[LOW1E:%v[0-9]+]], %v26, %v26328; CHECK-DAG: vldeb [[HIGH0D:%v[0-9]+]], [[HIGH0E]]329; CHECK-DAG: vldeb [[HIGH1D:%v[0-9]+]], [[HIGH1E]]330; CHECK-DAG: vldeb [[LOW0D:%v[0-9]+]], [[LOW0E]]331; CHECK-DAG: vldeb [[LOW1D:%v[0-9]+]], [[LOW1E]]332; CHECK-DAG: vfchedb [[HIGHRES0:%v[0-9]+]], [[HIGH0D]], [[HIGH1D]]333; CHECK-DAG: vfchedb [[LOWRES0:%v[0-9]+]], [[LOW0D]], [[LOW1D]]334; CHECK-DAG: vfchdb [[HIGHRES1:%v[0-9]+]], [[HIGH1D]], [[HIGH0D]]335; CHECK-DAG: vfchdb [[LOWRES1:%v[0-9]+]], [[LOW1D]], [[LOW0D]]336; CHECK-DAG: vpkg [[RES0:%v[0-9]+]], [[HIGHRES0]], [[LOWRES0]]337; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]338; CHECK: vno %v24, [[RES1]], [[RES0]]339; CHECK-NEXT: br %r14340 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(341 <4 x float> %val1, <4 x float> %val2,342 metadata !"uno",343 metadata !"fpexcept.strict") #0344 %ret = sext <4 x i1> %cmp to <4 x i32>345 ret <4 x i32> %ret346}347 348; Test oeq selects.349define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2,350 <4 x float> %val3, <4 x float> %val4) #0 {351; CHECK-LABEL: f15:352; CHECK: vpkg [[REG:%v[0-9]+]],353; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]354; CHECK-NEXT: br %r14355 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(356 <4 x float> %val1, <4 x float> %val2,357 metadata !"oeq",358 metadata !"fpexcept.strict") #0359 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4360 ret <4 x float> %ret361}362 363; Test one selects.364define <4 x float> @f16(<4 x float> %val1, <4 x float> %val2,365 <4 x float> %val3, <4 x float> %val4) #0 {366; CHECK-LABEL: f16:367; CHECK: vo [[REG:%v[0-9]+]],368; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]369; CHECK-NEXT: br %r14370 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(371 <4 x float> %val1, <4 x float> %val2,372 metadata !"one",373 metadata !"fpexcept.strict") #0374 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4375 ret <4 x float> %ret376}377 378; Test ogt selects.379define <4 x float> @f17(<4 x float> %val1, <4 x float> %val2,380 <4 x float> %val3, <4 x float> %val4) #0 {381; CHECK-LABEL: f17:382; CHECK: vpkg [[REG:%v[0-9]+]],383; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]384; CHECK-NEXT: br %r14385 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(386 <4 x float> %val1, <4 x float> %val2,387 metadata !"ogt",388 metadata !"fpexcept.strict") #0389 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4390 ret <4 x float> %ret391}392 393; Test oge selects.394define <4 x float> @f18(<4 x float> %val1, <4 x float> %val2,395 <4 x float> %val3, <4 x float> %val4) #0 {396; CHECK-LABEL: f18:397; CHECK: vpkg [[REG:%v[0-9]+]],398; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]399; CHECK-NEXT: br %r14400 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(401 <4 x float> %val1, <4 x float> %val2,402 metadata !"oge",403 metadata !"fpexcept.strict") #0404 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4405 ret <4 x float> %ret406}407 408; Test ole selects.409define <4 x float> @f19(<4 x float> %val1, <4 x float> %val2,410 <4 x float> %val3, <4 x float> %val4) #0 {411; CHECK-LABEL: f19:412; CHECK: vpkg [[REG:%v[0-9]+]],413; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]414; CHECK-NEXT: br %r14415 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(416 <4 x float> %val1, <4 x float> %val2,417 metadata !"ole",418 metadata !"fpexcept.strict") #0419 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4420 ret <4 x float> %ret421}422 423; Test olt selects.424define <4 x float> @f20(<4 x float> %val1, <4 x float> %val2,425 <4 x float> %val3, <4 x float> %val4) #0 {426; CHECK-LABEL: f20:427; CHECK: vpkg [[REG:%v[0-9]+]],428; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]429; CHECK-NEXT: br %r14430 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(431 <4 x float> %val1, <4 x float> %val2,432 metadata !"olt",433 metadata !"fpexcept.strict") #0434 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4435 ret <4 x float> %ret436}437 438; Test ueq selects.439define <4 x float> @f21(<4 x float> %val1, <4 x float> %val2,440 <4 x float> %val3, <4 x float> %val4) #0 {441; CHECK-LABEL: f21:442; CHECK: vo [[REG:%v[0-9]+]],443; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]444; CHECK-NEXT: br %r14445 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(446 <4 x float> %val1, <4 x float> %val2,447 metadata !"ueq",448 metadata !"fpexcept.strict") #0449 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4450 ret <4 x float> %ret451}452 453; Test une selects.454define <4 x float> @f22(<4 x float> %val1, <4 x float> %val2,455 <4 x float> %val3, <4 x float> %val4) #0 {456; CHECK-LABEL: f22:457; CHECK: vpkg [[REG:%v[0-9]+]],458; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]459; CHECK-NEXT: br %r14460 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(461 <4 x float> %val1, <4 x float> %val2,462 metadata !"une",463 metadata !"fpexcept.strict") #0464 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4465 ret <4 x float> %ret466}467 468; Test ugt selects.469define <4 x float> @f23(<4 x float> %val1, <4 x float> %val2,470 <4 x float> %val3, <4 x float> %val4) #0 {471; CHECK-LABEL: f23:472; CHECK: vpkg [[REG:%v[0-9]+]],473; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]474; CHECK-NEXT: br %r14475 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(476 <4 x float> %val1, <4 x float> %val2,477 metadata !"ugt",478 metadata !"fpexcept.strict") #0479 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4480 ret <4 x float> %ret481}482 483; Test uge selects.484define <4 x float> @f24(<4 x float> %val1, <4 x float> %val2,485 <4 x float> %val3, <4 x float> %val4) #0 {486; CHECK-LABEL: f24:487; CHECK: vpkg [[REG:%v[0-9]+]],488; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]489; CHECK-NEXT: br %r14490 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(491 <4 x float> %val1, <4 x float> %val2,492 metadata !"uge",493 metadata !"fpexcept.strict") #0494 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4495 ret <4 x float> %ret496}497 498; Test ule selects.499define <4 x float> @f25(<4 x float> %val1, <4 x float> %val2,500 <4 x float> %val3, <4 x float> %val4) #0 {501; CHECK-LABEL: f25:502; CHECK: vpkg [[REG:%v[0-9]+]],503; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]504; CHECK-NEXT: br %r14505 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(506 <4 x float> %val1, <4 x float> %val2,507 metadata !"ule",508 metadata !"fpexcept.strict") #0509 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4510 ret <4 x float> %ret511}512 513; Test ult selects.514define <4 x float> @f26(<4 x float> %val1, <4 x float> %val2,515 <4 x float> %val3, <4 x float> %val4) #0 {516; CHECK-LABEL: f26:517; CHECK: vpkg [[REG:%v[0-9]+]],518; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]519; CHECK-NEXT: br %r14520 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(521 <4 x float> %val1, <4 x float> %val2,522 metadata !"ult",523 metadata !"fpexcept.strict") #0524 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4525 ret <4 x float> %ret526}527 528; Test ord selects.529define <4 x float> @f27(<4 x float> %val1, <4 x float> %val2,530 <4 x float> %val3, <4 x float> %val4) #0 {531; CHECK-LABEL: f27:532; CHECK: vo [[REG:%v[0-9]+]],533; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]534; CHECK-NEXT: br %r14535 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(536 <4 x float> %val1, <4 x float> %val2,537 metadata !"ord",538 metadata !"fpexcept.strict") #0539 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4540 ret <4 x float> %ret541}542 543; Test uno selects.544define <4 x float> @f28(<4 x float> %val1, <4 x float> %val2,545 <4 x float> %val3, <4 x float> %val4) #0 {546; CHECK-LABEL: f28:547; CHECK: vo [[REG:%v[0-9]+]],548; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]549; CHECK-NEXT: br %r14550 %cmp = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(551 <4 x float> %val1, <4 x float> %val2,552 metadata !"uno",553 metadata !"fpexcept.strict") #0554 %ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4555 ret <4 x float> %ret556}557 558attributes #0 = { strictfp }559 560declare <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float>, <4 x float>, metadata, metadata)561