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1; Test vector subtraction.2;3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s4 5; Test a v16i8 subtraction.6define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {7; CHECK-LABEL: f1:8; CHECK: vsb %v24, %v26, %v289; CHECK: br %r1410 %ret = sub <16 x i8> %val1, %val211 ret <16 x i8> %ret12}13 14; Test a v8i16 subtraction.15define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {16; CHECK-LABEL: f2:17; CHECK: vsh %v24, %v26, %v2818; CHECK: br %r1419 %ret = sub <8 x i16> %val1, %val220 ret <8 x i16> %ret21}22 23; Test a v4i32 subtraction.24define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {25; CHECK-LABEL: f3:26; CHECK: vsf %v24, %v26, %v2827; CHECK: br %r1428 %ret = sub <4 x i32> %val1, %val229 ret <4 x i32> %ret30}31 32; Test a v2i64 subtraction.33define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {34; CHECK-LABEL: f4:35; CHECK: vsg %v24, %v26, %v2836; CHECK: br %r1437 %ret = sub <2 x i64> %val1, %val238 ret <2 x i64> %ret39}40 41; Test a v4f32 subtraction, as an example of an operation that needs to be42; scalarized and reassembled. At present there's an unnecessary move that43; could be avoided with smarter ordering. It also isn't important whether44; the VSLDBs use the result of the VLRs or use %v24 and %v26 directly.45define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {46; CHECK-LABEL: f5:47; CHECK-DAG: vlr %v[[A1:[0-5]]], %v2448; CHECK-DAG: vlr %v[[A2:[0-5]]], %v2649; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v24, 150; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v26, 151; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v24, 252; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v26, 253; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v24, 354; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v26, 355; CHECK-DAG: sebr %f[[A1]], %f[[A2]]56; CHECK-DAG: sebr %f[[B1]], %f[[B2]]57; CHECK-DAG: sebr %f[[C1]], %f[[C2]]58; CHECK-DAG: sebr %f[[D1]], %f[[D2]]59; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1]], %v[[B1]]60; CHECK-DAG: vmrhf [[LOW:%v[0-9]+]], %v[[C1]], %v[[D1]]61; CHECK: vmrhg %v24, [[HIGH]], [[LOW]]62; CHECK: br %r1463 %ret = fsub <4 x float> %val1, %val264 ret <4 x float> %ret65}66 67; Test a v2f64 subtraction.68define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,69 <2 x double> %val2) {70; CHECK-LABEL: f6:71; CHECK: vfsdb %v24, %v26, %v2872; CHECK: br %r1473 %ret = fsub <2 x double> %val1, %val274 ret <2 x double> %ret75}76 77; Test an f64 subtraction that uses vector registers.78define double @f7(<2 x double> %val1, <2 x double> %val2) {79; CHECK-LABEL: f7:80; CHECK: wfsdb %f0, %v24, %v2681; CHECK: br %r1482 %scalar1 = extractelement <2 x double> %val1, i32 083 %scalar2 = extractelement <2 x double> %val2, i32 084 %ret = fsub double %scalar1, %scalar285 ret double %ret86}87 88; Test a v2i8 subtraction, which gets promoted to v16i8.89define <2 x i8> @f8(<2 x i8> %dummy, <2 x i8> %val1, <2 x i8> %val2) {90; CHECK-LABEL: f8:91; CHECK: vsb %v24, %v26, %v2892; CHECK: br %r1493 %ret = sub <2 x i8> %val1, %val294 ret <2 x i8> %ret95}96 97; Test a v4i8 subtraction, which gets promoted to v16i8.98define <4 x i8> @f9(<4 x i8> %dummy, <4 x i8> %val1, <4 x i8> %val2) {99; CHECK-LABEL: f9:100; CHECK: vsb %v24, %v26, %v28101; CHECK: br %r14102 %ret = sub <4 x i8> %val1, %val2103 ret <4 x i8> %ret104}105 106; Test a v8i8 subtraction, which gets promoted to v16i8.107define <8 x i8> @f10(<8 x i8> %dummy, <8 x i8> %val1, <8 x i8> %val2) {108; CHECK-LABEL: f10:109; CHECK: vsb %v24, %v26, %v28110; CHECK: br %r14111 %ret = sub <8 x i8> %val1, %val2112 ret <8 x i8> %ret113}114 115; Test a v2i16 subtraction, which gets promoted to v8i16.116define <2 x i16> @f11(<2 x i16> %dummy, <2 x i16> %val1, <2 x i16> %val2) {117; CHECK-LABEL: f11:118; CHECK: vsh %v24, %v26, %v28119; CHECK: br %r14120 %ret = sub <2 x i16> %val1, %val2121 ret <2 x i16> %ret122}123 124; Test a v4i16 subtraction, which gets promoted to v8i16.125define <4 x i16> @f12(<4 x i16> %dummy, <4 x i16> %val1, <4 x i16> %val2) {126; CHECK-LABEL: f12:127; CHECK: vsh %v24, %v26, %v28128; CHECK: br %r14129 %ret = sub <4 x i16> %val1, %val2130 ret <4 x i16> %ret131}132 133; Test a v2i32 subtraction, which gets promoted to v4i32.134define <2 x i32> @f13(<2 x i32> %dummy, <2 x i32> %val1, <2 x i32> %val2) {135; CHECK-LABEL: f13:136; CHECK: vsf %v24, %v26, %v28137; CHECK: br %r14138 %ret = sub <2 x i32> %val1, %val2139 ret <2 x i32> %ret140}141 142; Test a v2f32 subtraction, which gets promoted to v4f32.143define <2 x float> @f14(<2 x float> %val1, <2 x float> %val2) {144; No particular output expected, but must compile.145 %ret = fsub <2 x float> %val1, %val2146 ret <2 x float> %ret147}148 149; Test a v1i128 subtraction.150define <1 x i128> @f15(<1 x i128> %dummy, <1 x i128> %val1, <1 x i128> %val2) {151; CHECK-LABEL: f15:152; CHECK: vsq %v24, %v26, %v28153; CHECK: br %r14154 %ret = sub <1 x i128> %val1, %val2155 ret <1 x i128> %ret156}157