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1; Test the generated function prologs/epilogs under XPLINK64 on z/OS2;3; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck --check-prefixes=CHECK64,CHECK %s4 5; Test prolog/epilog for non-XPLEAF.6 7; Small stack frame.8; CHECK-LABEL: func09; CHECK64: stmg 6,7,1872(4)10; stmg instruction's displacement field must be 2064-dsa_size11; as per ABI12; CHECK64: aghi 4,-19213 14; CHECK64: lg 7,2072(4)15; CHECK64: aghi 4,19216; CHECK64: b 2(7)17 18; CHECK64: L#PPA1_func0_0:19; CHECK64: .short 0 * Length/4 of Parms20define void @func0() {21 call i64 (i64) @fun(i64 10) 22 ret void23}24 25; Spill all GPR CSRs26; CHECK-LABEL: func127; CHECK64: stmg 6,15,1904(4)28; CHECK64: aghi 4,-16029 30; CHECK64: lmg 7,15,2072(4)31; CHECK64: aghi 4,16032; CHECK64: b 2(7)33 34; CHECK64: L#PPA1_func1_0:35; CHECK64: .short 2 * Length/4 of Parms36define void @func1(ptr %ptr) {37 %l01 = load volatile i64, ptr %ptr38 %l02 = load volatile i64, ptr %ptr39 %l03 = load volatile i64, ptr %ptr40 %l04 = load volatile i64, ptr %ptr41 %l05 = load volatile i64, ptr %ptr42 %l06 = load volatile i64, ptr %ptr43 %l07 = load volatile i64, ptr %ptr44 %l08 = load volatile i64, ptr %ptr45 %l09 = load volatile i64, ptr %ptr46 %l10 = load volatile i64, ptr %ptr47 %l11 = load volatile i64, ptr %ptr48 %l12 = load volatile i64, ptr %ptr49 %l13 = load volatile i64, ptr %ptr50 %l14 = load volatile i64, ptr %ptr51 %l15 = load volatile i64, ptr %ptr52 %add01 = add i64 %l01, %l0153 %add02 = add i64 %l02, %add0154 %add03 = add i64 %l03, %add0255 %add04 = add i64 %l04, %add0356 %add05 = add i64 %l05, %add0457 %add06 = add i64 %l06, %add0558 %add07 = add i64 %l07, %add0659 %add08 = add i64 %l08, %add0760 %add09 = add i64 %l09, %add0861 %add10 = add i64 %l10, %add0962 %add11 = add i64 %l11, %add1063 %add12 = add i64 %l12, %add1164 %add13 = add i64 %l13, %add1265 %add14 = add i64 %l14, %add1366 %add15 = add i64 %l15, %add1467 store volatile i64 %add01, ptr %ptr68 store volatile i64 %add02, ptr %ptr69 store volatile i64 %add03, ptr %ptr70 store volatile i64 %add04, ptr %ptr71 store volatile i64 %add05, ptr %ptr72 store volatile i64 %add06, ptr %ptr73 store volatile i64 %add07, ptr %ptr74 store volatile i64 %add08, ptr %ptr75 store volatile i64 %add09, ptr %ptr76 store volatile i64 %add10, ptr %ptr77 store volatile i64 %add11, ptr %ptr78 store volatile i64 %add12, ptr %ptr79 store volatile i64 %add13, ptr %ptr80 store volatile i64 %add14, ptr %ptr81 store volatile i64 %add15, ptr %ptr82 ret void83}84 85 86; Spill all FPRs and VRs87; CHECK-LABEL: func288; CHECK64: stmg 6,7,1744(4)89; CHECK64: aghi 4,-32090; CHECK64: std 15,{{[0-9]+}}(4) * 8-byte Spill91; CHECK64: std 14,{{[0-9]+}}(4) * 8-byte Spill92; CHECK64: std 13,{{[0-9]+}}(4) * 8-byte Spill93; CHECK64: std 12,{{[0-9]+}}(4) * 8-byte Spill94; CHECK64: std 11,{{[0-9]+}}(4) * 8-byte Spill95; CHECK64: std 10,{{[0-9]+}}(4) * 8-byte Spill96; CHECK64: std 9,{{[0-9]+}}(4) * 8-byte Spill97; CHECK64: std 8,{{[0-9]+}}(4) * 8-byte Spill98; CHECK64: vst 23,{{[0-9]+}}(4),4 * 16-byte Spill99; CHECK64: vst 22,{{[0-9]+}}(4),4 * 16-byte Spill100; CHECK64: vst 21,{{[0-9]+}}(4),4 * 16-byte Spill101; CHECK64: vst 20,{{[0-9]+}}(4),4 * 16-byte Spill102; CHECK64: vst 19,{{[0-9]+}}(4),4 * 16-byte Spill103; CHECK64: vst 18,{{[0-9]+}}(4),4 * 16-byte Spill104; CHECK64: vst 17,{{[0-9]+}}(4),4 * 16-byte Spill105; CHECK64: vst 16,{{[0-9]+}}(4),4 * 16-byte Spill106 107; CHECK64: ld 15,{{[0-9]+}}(4) * 8-byte Reload108; CHECK64: ld 14,{{[0-9]+}}(4) * 8-byte Reload109; CHECK64: ld 13,{{[0-9]+}}(4) * 8-byte Reload110; CHECK64: ld 12,{{[0-9]+}}(4) * 8-byte Reload111; CHECK64: ld 11,{{[0-9]+}}(4) * 8-byte Reload112; CHECK64: ld 10,{{[0-9]+}}(4) * 8-byte Reload113; CHECK64: ld 9,{{[0-9]+}}(4) * 8-byte Reload114; CHECK64: ld 8,{{[0-9]+}}(4) * 8-byte Reload115; CHECK64: vl 23,{{[0-9]+}}(4),4 * 16-byte Reload116; CHECK64: vl 22,{{[0-9]+}}(4),4 * 16-byte Reload117; CHECK64: vl 21,{{[0-9]+}}(4),4 * 16-byte Reload118; CHECK64: vl 20,{{[0-9]+}}(4),4 * 16-byte Reload119; CHECK64: vl 19,{{[0-9]+}}(4),4 * 16-byte Reload120; CHECK64: vl 18,{{[0-9]+}}(4),4 * 16-byte Reload121; CHECK64: vl 17,{{[0-9]+}}(4),4 * 16-byte Reload122; CHECK64: vl 16,{{[0-9]+}}(4),4 * 16-byte Reload123; CHECK64: lg 7,2072(4)124; CHECK64: aghi 4,320125; CHECK64: b 2(7)126 127define void @func2(ptr %ptr, ptr %vec_ptr) {128 %l00 = load volatile double, ptr %ptr129 %l01 = load volatile double, ptr %ptr130 %l02 = load volatile double, ptr %ptr131 %l03 = load volatile double, ptr %ptr132 %l04 = load volatile double, ptr %ptr133 %l05 = load volatile double, ptr %ptr134 %l06 = load volatile double, ptr %ptr135 %l07 = load volatile double, ptr %ptr136 %l08 = load volatile double, ptr %ptr137 %l09 = load volatile double, ptr %ptr138 %l10 = load volatile double, ptr %ptr139 %l11 = load volatile double, ptr %ptr140 %l12 = load volatile double, ptr %ptr141 %l13 = load volatile double, ptr %ptr142 %l14 = load volatile double, ptr %ptr143 %l15 = load volatile double, ptr %ptr144 %add00 = fadd double %l01, %l00145 %add01 = fadd double %l01, %add00146 %add02 = fadd double %l02, %add01147 %add03 = fadd double %l03, %add02148 %add04 = fadd double %l04, %add03149 %add05 = fadd double %l05, %add04150 %add06 = fadd double %l06, %add05151 %add07 = fadd double %l07, %add06152 %add08 = fadd double %l08, %add07153 %add09 = fadd double %l09, %add08154 %add10 = fadd double %l10, %add09155 %add11 = fadd double %l11, %add10156 %add12 = fadd double %l12, %add11157 %add13 = fadd double %l13, %add12158 %add14 = fadd double %l14, %add13159 %add15 = fadd double %l15, %add14160 store volatile double %add00, ptr %ptr161 store volatile double %add01, ptr %ptr162 store volatile double %add02, ptr %ptr163 store volatile double %add03, ptr %ptr164 store volatile double %add04, ptr %ptr165 store volatile double %add05, ptr %ptr166 store volatile double %add06, ptr %ptr167 store volatile double %add07, ptr %ptr168 store volatile double %add08, ptr %ptr169 store volatile double %add09, ptr %ptr170 store volatile double %add10, ptr %ptr171 store volatile double %add11, ptr %ptr172 store volatile double %add12, ptr %ptr173 store volatile double %add13, ptr %ptr174 store volatile double %add14, ptr %ptr175 store volatile double %add15, ptr %ptr176 177 %v00 = load volatile <2 x i64>, ptr %vec_ptr178 %v01 = load volatile <2 x i64>, ptr %vec_ptr179 %v02 = load volatile <2 x i64>, ptr %vec_ptr180 %v03 = load volatile <2 x i64>, ptr %vec_ptr181 %v04 = load volatile <2 x i64>, ptr %vec_ptr182 %v05 = load volatile <2 x i64>, ptr %vec_ptr183 %v06 = load volatile <2 x i64>, ptr %vec_ptr184 %v07 = load volatile <2 x i64>, ptr %vec_ptr185 %v08 = load volatile <2 x i64>, ptr %vec_ptr186 %v09 = load volatile <2 x i64>, ptr %vec_ptr187 %v10 = load volatile <2 x i64>, ptr %vec_ptr188 %v11 = load volatile <2 x i64>, ptr %vec_ptr189 %v12 = load volatile <2 x i64>, ptr %vec_ptr190 %v13 = load volatile <2 x i64>, ptr %vec_ptr191 %v14 = load volatile <2 x i64>, ptr %vec_ptr192 %v15 = load volatile <2 x i64>, ptr %vec_ptr193 %v16 = load volatile <2 x i64>, ptr %vec_ptr194 %v17 = load volatile <2 x i64>, ptr %vec_ptr195 %v18 = load volatile <2 x i64>, ptr %vec_ptr196 %v19 = load volatile <2 x i64>, ptr %vec_ptr197 %v20 = load volatile <2 x i64>, ptr %vec_ptr198 %v21 = load volatile <2 x i64>, ptr %vec_ptr199 %v22 = load volatile <2 x i64>, ptr %vec_ptr200 %v23 = load volatile <2 x i64>, ptr %vec_ptr201 %v24 = load volatile <2 x i64>, ptr %vec_ptr202 %v25 = load volatile <2 x i64>, ptr %vec_ptr203 %v26 = load volatile <2 x i64>, ptr %vec_ptr204 %v27 = load volatile <2 x i64>, ptr %vec_ptr205 %v28 = load volatile <2 x i64>, ptr %vec_ptr206 %v29 = load volatile <2 x i64>, ptr %vec_ptr207 %v30 = load volatile <2 x i64>, ptr %vec_ptr208 %v31 = load volatile <2 x i64>, ptr %vec_ptr209 %vadd00 = add <2 x i64> %v00, %v00210 %vadd01 = add <2 x i64> %v01, %vadd00211 %vadd02 = add <2 x i64> %v02, %vadd01212 %vadd03 = add <2 x i64> %v03, %vadd02213 %vadd04 = add <2 x i64> %v04, %vadd03214 %vadd05 = add <2 x i64> %v05, %vadd04215 %vadd06 = add <2 x i64> %v06, %vadd05216 %vadd07 = add <2 x i64> %v07, %vadd06217 %vadd08 = add <2 x i64> %v08, %vadd07218 %vadd09 = add <2 x i64> %v09, %vadd08219 %vadd10 = add <2 x i64> %v10, %vadd09220 %vadd11 = add <2 x i64> %v11, %vadd10221 %vadd12 = add <2 x i64> %v12, %vadd11222 %vadd13 = add <2 x i64> %v13, %vadd12223 %vadd14 = add <2 x i64> %v14, %vadd13224 %vadd15 = add <2 x i64> %v15, %vadd14225 %vadd16 = add <2 x i64> %v16, %vadd15226 %vadd17 = add <2 x i64> %v17, %vadd16227 %vadd18 = add <2 x i64> %v18, %vadd17228 %vadd19 = add <2 x i64> %v19, %vadd18229 %vadd20 = add <2 x i64> %v20, %vadd19230 %vadd21 = add <2 x i64> %v21, %vadd20231 %vadd22 = add <2 x i64> %v22, %vadd21232 %vadd23 = add <2 x i64> %v23, %vadd22233 %vadd24 = add <2 x i64> %v24, %vadd23234 %vadd25 = add <2 x i64> %v25, %vadd24235 %vadd26 = add <2 x i64> %v26, %vadd25236 %vadd27 = add <2 x i64> %v27, %vadd26237 %vadd28 = add <2 x i64> %v28, %vadd27238 %vadd29 = add <2 x i64> %v29, %vadd28239 %vadd30 = add <2 x i64> %v30, %vadd29240 %vadd31 = add <2 x i64> %v31, %vadd30241 store volatile <2 x i64> %vadd00, ptr %vec_ptr242 store volatile <2 x i64> %vadd01, ptr %vec_ptr243 store volatile <2 x i64> %vadd02, ptr %vec_ptr244 store volatile <2 x i64> %vadd03, ptr %vec_ptr245 store volatile <2 x i64> %vadd04, ptr %vec_ptr246 store volatile <2 x i64> %vadd05, ptr %vec_ptr247 store volatile <2 x i64> %vadd06, ptr %vec_ptr248 store volatile <2 x i64> %vadd07, ptr %vec_ptr249 store volatile <2 x i64> %vadd08, ptr %vec_ptr250 store volatile <2 x i64> %vadd09, ptr %vec_ptr251 store volatile <2 x i64> %vadd10, ptr %vec_ptr252 store volatile <2 x i64> %vadd11, ptr %vec_ptr253 store volatile <2 x i64> %vadd12, ptr %vec_ptr254 store volatile <2 x i64> %vadd13, ptr %vec_ptr255 store volatile <2 x i64> %vadd14, ptr %vec_ptr256 store volatile <2 x i64> %vadd15, ptr %vec_ptr257 store volatile <2 x i64> %vadd16, ptr %vec_ptr258 store volatile <2 x i64> %vadd17, ptr %vec_ptr259 store volatile <2 x i64> %vadd18, ptr %vec_ptr260 store volatile <2 x i64> %vadd19, ptr %vec_ptr261 store volatile <2 x i64> %vadd20, ptr %vec_ptr262 store volatile <2 x i64> %vadd21, ptr %vec_ptr263 store volatile <2 x i64> %vadd22, ptr %vec_ptr264 store volatile <2 x i64> %vadd23, ptr %vec_ptr265 store volatile <2 x i64> %vadd24, ptr %vec_ptr266 store volatile <2 x i64> %vadd25, ptr %vec_ptr267 store volatile <2 x i64> %vadd26, ptr %vec_ptr268 store volatile <2 x i64> %vadd27, ptr %vec_ptr269 store volatile <2 x i64> %vadd28, ptr %vec_ptr270 store volatile <2 x i64> %vadd29, ptr %vec_ptr271 store volatile <2 x i64> %vadd30, ptr %vec_ptr272 store volatile <2 x i64> %vadd31, ptr %vec_ptr273 ret void274}275 276; Big stack frame, force the use of agfi before stmg277; despite not requiring stack extension routine.278; CHECK64: agfi 4,-1040768279; CHECK64: stmg 6,7,2064(4)280; CHECK64: agfi 4,1040768281define void @func3() {282 %arr = alloca [130070 x i64], align 8283 call i64 (ptr) @fun1(ptr %arr)284 ret void285}286 287; Requires the saving of r4 due to variable sized288; object in stack frame. (Eg: VLA) Sets up frame pointer in r8289; CHECK64: stmg 4,10,1856(4)290; CHECK64: aghi 4,-192291; CHECK64: lg 6,40(5)292; CHECK64: lg 5,32(5)293; CHECK64: lgr 8,4294; CHECK64: basr 7,6295; CHECK64-NEXT: bcr 0,0296; CHECK64: lmg 4,10,2048(4)297define i64 @func4(i64 %n) {298 %vla = alloca i64, i64 %n, align 8299 %call = call i64 @fun2(i64 %n, ptr nonnull %vla, ptr nonnull %vla)300 ret i64 %call301}302 303; Require saving of r4 and in addition, a displacement large enough304; to force use of agfi before stmg.305; CHECK64: lgr 0,4306; CHECK64: agfi 4,-1040224307; CHECK64: stmg 4,10,2048(4)308; CHECK64: lgr 8,4309; CHECK64: basr 7,6310; CHECK64-NEXT: bcr 0,0311; CHECK64: lmg 4,10,2048(4)312define i64 @func5(i64 %n) {313 %vla = alloca i64, i64 %n, align 8314 %arr = alloca [130000 x i64], align 8315 %call = call i64 @fun2(i64 %n, ptr nonnull %vla, ptr %arr)316 ret i64 %call317}318 319; CHECK-LABEL: large_stack320; CHECK64: agfi 4,-1048800321; CHECK64-NEXT: llgt 3,1208322; CHECK64-NEXT: cg 4,64(3)323; CHECK64-NEXT: jhe324; CHECK64: * %bb.1:325; CHECK64: lg 3,72(3)326; CHECK64: basr 3,3327; CHECK64: stmg 6,7,2064(4)328define void @large_stack0() {329 %arr = alloca [131072 x i64], align 8330 call i64 (ptr) @fun1(ptr %arr)331 ret void332}333 334; CHECK-LABEL: large_stack1335; CHECK64: agfi 4,-1048800336; CHECK64: lgr 0,3337; CHECK64: llgt 3,1208338; CHECK64: cg 4,64(3)339; CHECK64: jhe L#BB7_2340; CHECK64: %bb.1:341; CHECK64: lg 3,72(3)342; CHECK64: basr 3,3343; CHECK64: bcr 0,7344; CHECK64: L#BB7_2:345; CHECK64: stmg 6,7,2064(4)346; CHECK64: lgr 3,0347 348; CHECK64: L#PPA1_large_stack1_0:349; CHECK64: .short 6 * Length/4 of Parms350define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {351 %arr = alloca [131072 x i64], align 8352 call i64 (ptr, i64, i64, i64) @fun3(ptr %arr,353 i64 %n1, i64 %n2, i64 %n3)354 ret void355}356 357 358; CHECK-LABEL: large_stack2359; CHECK64: lgr 0,4360; CHECK64: stg 3,2192(4)361; CHECK64: agfi 4,-1048800362; CHECK64: llgt 3,1208363; CHECK64: cg 4,64(3)364; CHECK64: jhe L#BB8_2365; CHECK64: %bb.1:366; CHECK64: lg 3,72(3)367; CHECK64: basr 3,3368; CHECK64: bcr 0,7369; CHECK64: L#BB8_2:370; CHECK64: lgr 3,0371; CHECK64: lg 3,2192(3)372; CHECK64: stmg 4,12,2048(4)373; CHECK64: lgr 8,4374define void @large_stack2(i64 %n1, i64 %n2, i64 %n3) {375 %arr0 = alloca [131072 x i64], align 8376 %arr1 = alloca i64, i64 %n1, align 8377 call i64 (ptr, ptr, i64, i64, i64) @fun4(ptr %arr0,378 ptr %arr1, i64 %n1, i64 %n2, i64 %n3)379 ret void380}381 382; CHECK-LABEL: leaf_func383; CHECK: .long 8 * DSA Size 0x0384; CHECK-NEXT: * Entry Flags385; CHECK-NEXT: * Bit 1: 1 = Leaf function386; CHECK-NEXT: * Bit 2: 0 = Does not use alloca387; CHECK-NOT: aghi 4,388; CHECK-NOT: stmg389; CHECK: agr 1,2390; CHECK: msgr 1,3391; CHECK: aghik 3,1,-4392; CHECK-NOT: aghi 4,393; CHECK-NOT: lmg394define i64 @leaf_func0(i64 %a, i64 %b, i64 %c) {395 %n = add i64 %a, %b396 %m = mul i64 %n, %c397 %o = sub i64 %m, 4398 ret i64 %o399}400 401 402; =============================403; Tests for PPA1 Fields404; =============================405; CHECK-LABEL: named_func406; CHECK: .byte 129 * PPA1 Flags 4407; CHECK-NEXT: * Bit 7: 1 = Name Length and Name408define i64 @named_func(i64 %arg) {409 %sum = add i64 1, %arg410 ret i64 %sum411}412 413; CHECK-LABEL: __unnamed_1414; CHECK: .byte 128 * PPA1 Flags 4415; CHECK-NOT: * Bit 7: 1 = Name Length and Name416define void @""(ptr %p) {417 call i64 (ptr) @fun1(ptr %p)418 ret void419}420 421 422declare i64 @fun(i64 %arg0)423declare i64 @fun1(ptr %ptr)424declare i64 @fun2(i64 %n, ptr %arr0, ptr %arr1)425declare i64 @fun3(ptr %ptr, i64 %n1, i64 %n2, i64 %n3)426declare i64 @fun4(ptr %ptr0, ptr %ptr1, i64 %n1, i64 %n2, i64 %n3)427